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UefiPayloadPkg: Modify PCI root reg . 

Per Spec updated , update DMA Reg property filed
with each root bridge bus base and its bus limit.

Signed-off-by: Linus Liu <linus.liu@intel.com>
This commit is contained in:
Linus Liu 2024-09-12 21:22:30 -07:00 committed by mergify[bot]
parent aac5b3eca3
commit de19273e89
1 changed files with 14 additions and 4 deletions
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18
UefiPayloadPkg/Library/BuildFdtLib/X86_BuildFdtLib.c
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@ -404,6 +404,7 @@ BuildFdtForPciRootBridge (
UINT32 RegTmp[2];
UINT32 RegData[21];
UINT32 DMARegData[8];
UINT64 Reg64Data[2];
UINT32 Data32;
UINT64 Data64;
UINT8 BusNumber;
@ -611,11 +612,14 @@ BuildFdtForPciRootBridge (
Status = FdtSetProperty (Fdt, TempNode, "dma-ranges", &DMARegData, sizeof (DMARegData));
ASSERT_EFI_ERROR (Status);
Data32 = CpuToFdt32 (2);
Status = FdtSetProperty (Fdt, TempNode, "#size-cells", &Data32, sizeof (UINT32));
ASSERT (PciRootBridgeInfo->RootBridge[Index].Bus.Base <= 0xFF);
ASSERT (PciRootBridgeInfo->RootBridge[Index].Bus.Limit <= 0xFF);
Data32 = CpuToFdt32 (3);
Status = FdtSetProperty (Fdt, TempNode, "#address-cells", &Data32, sizeof (UINT32));
Reg64Data[0] = CpuToFdt64 (PciExpressBaseAddress + LShiftU64 (PciRootBridgeInfo->RootBridge[Index].Bus.Base, 20));
Reg64Data[1] = CpuToFdt64 (LShiftU64 (PciRootBridgeInfo->RootBridge[Index].Bus.Limit +1, 20));
Status = FdtSetProperty (Fdt, TempNode, "reg", &Reg64Data, sizeof (Reg64Data));
ASSERT_EFI_ERROR (Status);
BusNumber = PciRootBridgeInfo->RootBridge[Index].Bus.Base & 0xFF;
RegTmp[0] = CpuToFdt32 (BusNumber);
@ -627,6 +631,12 @@ BuildFdtForPciRootBridge (
Status = FdtSetProperty (Fdt, TempNode, "bus-range", &RegTmp, sizeof (RegTmp));
ASSERT_EFI_ERROR (Status);
Data32 = CpuToFdt32 (2);
Status = FdtSetProperty (Fdt, TempNode, "#size-cells", &Data32, sizeof (UINT32));
Data32 = CpuToFdt32 (3);
Status = FdtSetProperty (Fdt, TempNode, "#address-cells", &Data32, sizeof (UINT32));
Status = FdtSetProperty (Fdt, TempNode, "compatible", "pci-rb", (UINT32)(AsciiStrLen ("pci-rb")+1));
ASSERT_EFI_ERROR (Status);