IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to building
error. when a module built-in X64 function pointer will be the size of
64bit width which cannot be fit in 32bit address which will lead to
error. to overcome this issue introducing the 2 new PCD's for the 64bit
modules can consume it. based on the which pcd platform set, use that.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Kuo Ted <ted.kuo@intel.com>
Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Digant H Solanki <digant.h.solanki@intel.com>
Cc: Sangeetha V <sangeetha.v@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
This commit is contained in:
S, Ashraf Ali 2021-12-16 16:10:20 +08:00 committed by mergify[bot]
parent ee1f8262b8
commit de9e5b7dc7
5 changed files with 56 additions and 8 deletions

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@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -38,6 +38,25 @@
extern EFI_GUID gFspHobGuid;
/**
Get the FSP M UPD Data address
@return FSP-M UPD Data Address
**/
UINTN
EFIAPI
GetFspmUpdDataAddress (
VOID
)
{
if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);
} else {
return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);
}
}
/**
Call FspMemoryInit API.
@ -67,7 +86,7 @@ PeiFspMemoryInit (
return EFI_DEVICE_ERROR;
}
if ((PcdGet32 (PcdFspmUpdDataAddress) == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
if ((GetFspmUpdDataAddress () == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
//
// Copy default FSP-M UPD data from Flash
//
@ -79,7 +98,7 @@ PeiFspMemoryInit (
//
// External UPD is ready, get the buffer from PCD pointer.
//
FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();
ASSERT (FspmUpdDataPtr != NULL);
}

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@ -6,7 +6,7 @@
# register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
# notify to call FspSiliconInit API.
#
# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -60,6 +60,7 @@
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64 ## CONSUMES
[Sources]
FspmWrapperPeim.c

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@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -181,6 +181,25 @@ FspSiliconInitDoneGetFspHobList (
}
}
/**
Get the FSP S UPD Data address
@return FSP-S UPD Data Address
**/
UINTN
EFIAPI
GetFspsUpdDataAddress (
VOID
)
{
if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64);
} else {
return (UINTN) PcdGet32 (PcdFspsUpdDataAddress);
}
}
/**
This function is for FSP dispatch mode to perform post FSP-S process.
@ -283,7 +302,7 @@ PeiMemoryDiscoveredNotify (
return EFI_DEVICE_ERROR;
}
if ((PcdGet32 (PcdFspsUpdDataAddress) == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
if ((GetFspsUpdDataAddress () == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
//
// Copy default FSP-S UPD data from Flash
//
@ -292,7 +311,7 @@ PeiMemoryDiscoveredNotify (
SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
} else {
FspsUpdDataPtr = (FSPS_UPD_COMMON *)PcdGet32 (PcdFspsUpdDataAddress);
FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress();
ASSERT (FspsUpdDataPtr != NULL);
}

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@ -6,7 +6,7 @@
# register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
# notify to call FspSiliconInit API.
#
# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -68,6 +68,7 @@
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64 ## CONSUMES
[Guids]
gFspHobGuid ## CONSUMES ## HOB

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@ -121,3 +121,11 @@
#
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001
#
# Non-0 means PcdFspmUpdDataAddress will be ignored, otherwise PcdFspmUpdDataAddress will be used.
#
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64|0x00000000|UINT64|0x50000002
#
# Non-0 means PcdFspsUpdDataAddress will be ignored, otherwise PcdFspsUpdDataAddress will be used.
#
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64|0x00000000|UINT64|0x50000003