mirror of https://github.com/acidanthera/audk.git
IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642 when the module is not building in IA32 mode which will lead to building error. when a module built-in X64 function pointer will be the size of 64bit width which cannot be fit in 32bit address which will lead to error. to overcome this issue introducing the 2 new PCD's for the 64bit modules can consume it. based on the which pcd platform set, use that. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Kuo Ted <ted.kuo@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Digant H Solanki <digant.h.solanki@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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@ -3,7 +3,7 @@
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register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
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notify to call FspSiliconInit API.
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Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -38,6 +38,25 @@
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extern EFI_GUID gFspHobGuid;
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/**
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Get the FSP M UPD Data address
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@return FSP-M UPD Data Address
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**/
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UINTN
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EFIAPI
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GetFspmUpdDataAddress (
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VOID
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)
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{
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if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) {
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return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64);
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} else {
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return (UINTN) PcdGet32 (PcdFspmUpdDataAddress);
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}
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}
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/**
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Call FspMemoryInit API.
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@ -67,7 +86,7 @@ PeiFspMemoryInit (
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return EFI_DEVICE_ERROR;
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}
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if ((PcdGet32 (PcdFspmUpdDataAddress) == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
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if ((GetFspmUpdDataAddress () == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
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//
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// Copy default FSP-M UPD data from Flash
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//
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@ -79,7 +98,7 @@ PeiFspMemoryInit (
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//
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// External UPD is ready, get the buffer from PCD pointer.
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//
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FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
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FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress();
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ASSERT (FspmUpdDataPtr != NULL);
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}
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@ -6,7 +6,7 @@
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# register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
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# notify to call FspSiliconInit API.
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#
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# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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@ -60,6 +60,7 @@
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
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gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64 ## CONSUMES
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[Sources]
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FspmWrapperPeim.c
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@ -3,7 +3,7 @@
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register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
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notify to call FspSiliconInit API.
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Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -181,6 +181,25 @@ FspSiliconInitDoneGetFspHobList (
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}
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}
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/**
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Get the FSP S UPD Data address
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@return FSP-S UPD Data Address
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**/
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UINTN
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EFIAPI
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GetFspsUpdDataAddress (
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VOID
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)
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{
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if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
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return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64);
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} else {
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return (UINTN) PcdGet32 (PcdFspsUpdDataAddress);
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}
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}
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/**
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This function is for FSP dispatch mode to perform post FSP-S process.
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@ -283,7 +302,7 @@ PeiMemoryDiscoveredNotify (
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return EFI_DEVICE_ERROR;
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}
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if ((PcdGet32 (PcdFspsUpdDataAddress) == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
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if ((GetFspsUpdDataAddress () == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
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//
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// Copy default FSP-S UPD data from Flash
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//
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@ -292,7 +311,7 @@ PeiMemoryDiscoveredNotify (
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SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
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CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
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} else {
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FspsUpdDataPtr = (FSPS_UPD_COMMON *)PcdGet32 (PcdFspsUpdDataAddress);
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FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress();
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ASSERT (FspsUpdDataPtr != NULL);
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}
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@ -6,7 +6,7 @@
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# register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
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# notify to call FspSiliconInit API.
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#
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# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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@ -68,6 +68,7 @@
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64 ## CONSUMES
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[Guids]
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gFspHobGuid ## CONSUMES ## HOB
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@ -121,3 +121,11 @@
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001
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#
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# Non-0 means PcdFspmUpdDataAddress will be ignored, otherwise PcdFspmUpdDataAddress will be used.
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64|0x00000000|UINT64|0x50000002
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#
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# Non-0 means PcdFspsUpdDataAddress will be ignored, otherwise PcdFspsUpdDataAddress will be used.
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#
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gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64|0x00000000|UINT64|0x50000003
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