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MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA

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PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE
attribute if the controller supports 64-bit DMA addressing.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
This commit is contained in:
Ard Biesheuvel 2016-09-05 09:51:48 +01:00
parent 4e28ea2c29
commit df0a0e4b6f
1 changed files with 20 additions and 0 deletions
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20
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
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@ -527,6 +527,7 @@ SdMmcPciHcDriverBindingStart (
CARD_TYPE_DETECT_ROUTINE *Routine; CARD_TYPE_DETECT_ROUTINE *Routine;
UINT32 RoutineNum; UINT32 RoutineNum;
BOOLEAN MediaPresent; BOOLEAN MediaPresent;
BOOLEAN Support64BitDma;
DEBUG ((EFI_D_INFO, "SdMmcPciHcDriverBindingStart: Start\n")); DEBUG ((EFI_D_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@ -600,6 +601,7 @@ SdMmcPciHcDriverBindingStart (
goto Done; goto Done;
} }
Support64BitDma = TRUE;
for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) { for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) {
Private->Slot[Slot].Enable = TRUE; Private->Slot[Slot].Enable = TRUE;
@ -609,6 +611,8 @@ SdMmcPciHcDriverBindingStart (
} }
DumpCapabilityReg (Slot, &Private->Capability[Slot]); DumpCapabilityReg (Slot, &Private->Capability[Slot]);
Support64BitDma &= Private->Capability[Slot].SysBus64;
Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
continue; continue;
@ -663,6 +667,22 @@ SdMmcPciHcDriverBindingStart (
} }
} }
//
// Enable 64-bit DMA support in the PCI layer if this controller
// supports it.
//
if (Support64BitDma) {
Status = PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationEnable,
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
NULL
);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_WARN, "SdMmcPciHcDriverBindingStart: failed to enable 64-bit DMA (%r)\n", Status));
}
}
// //
// Start the asynchronous I/O monitor // Start the asynchronous I/O monitor
// //