From df1c7e91b46db364ba1ce5e21660987c29c35334 Mon Sep 17 00:00:00 2001
From: "Duggapu, Chinni B" <chinni.b.duggapu@intel.com>
Date: Tue, 17 May 2022 16:44:01 +0800
Subject: [PATCH] IntelFsp2WrapperPkg: FSP_TEMP_RAM_INIT call for X64 Calling
 Convention

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926
Pass Input parameters using RCX.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: cbduggap <chinni.b.duggapu@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Ted Kuo <ted.kuo@intel.com>
---
 .../SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm       | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
index dbbf63336e..e3e62c31ce 100644
--- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
+++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/X64/SecEntry.nasm
@@ -130,6 +130,9 @@ FspHeaderFound:
   mov     eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
   add     eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
 
+  ; Pass Fsp T Upd pointer as Input parameter
+  mov     rcx, ASM_PFX(FsptUpdDataPtr)
+
   ; Setup the hardcode stack
   mov     rsp, TempRamInitStack
 
@@ -167,5 +170,4 @@ FspApiFailed:
 align 10h
 TempRamInitStack:
     DQ  TempRamInitDone
-    DQ  ASM_PFX(FsptUpdDataPtr)         ; TempRamInitParams