mirror of https://github.com/acidanthera/audk.git
ArmPkg/CpuDxe ARM: avoid splitting page table sections unnecessarily
Currently, any range passed to CpuArchProtocol::SetMemoryAttributes is fully broken down into page mappings if the start or the size of the region happens to be misaliged relative to the section size of 1 MB. This is going to result in memory being wasted on second level page tables when we enable strict memory permissions, given that we remap the entire RAM space non-executable (modulo the code bits) when the CpuArchProtocol is installed. So refactor the code to iterate over the range in a way that ensures that all naturally aligned section sized subregions are not broken up. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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@ -679,6 +679,11 @@ SetMemoryAttributes (
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)
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{
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EFI_STATUS Status;
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UINT64 ChunkLength;
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if (Length == 0) {
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return EFI_SUCCESS;
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}
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//
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// Ignore invocations that only modify permission bits
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@ -687,14 +692,44 @@ SetMemoryAttributes (
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return EFI_SUCCESS;
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}
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if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
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// Is the base and length a multiple of 1 MB?
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DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
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Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
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} else {
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// Base and/or length is not a multiple of 1 MB
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DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
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Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
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while (Length > 0) {
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if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
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Length >= TT_DESCRIPTOR_SECTION_SIZE) {
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ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;
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DEBUG ((DEBUG_PAGE,
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"SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
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BaseAddress, ChunkLength, Attributes));
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Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes,
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VirtualMask);
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} else {
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//
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// Process page by page until the next section boundary, but only if
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// we have more than a section's worth of area to deal with after that.
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//
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ChunkLength = TT_DESCRIPTOR_SECTION_SIZE -
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(BaseAddress % TT_DESCRIPTOR_SECTION_SIZE);
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if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) {
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ChunkLength = Length;
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}
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DEBUG ((DEBUG_PAGE,
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"SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
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BaseAddress, ChunkLength, Attributes));
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Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,
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VirtualMask);
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}
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if (EFI_ERROR (Status)) {
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break;
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}
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BaseAddress += ChunkLength;
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Length -= ChunkLength;
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}
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// Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
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