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UefiCpuPkg/PiSmmCpuDxeSmm: Enable/Restore XD in SMM
If XD is supported, then SMM enables it. The non-SMM execution environment can choose to enable or disable XD, so the state of XD must be detected in each SMI and be enabled/restored. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
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@ -1,7 +1,7 @@
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/** @file
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/** @file
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SMM MP service implementation
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SMM MP service implementation
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Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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which accompanies this distribution. The full text of the license may be found at
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@ -1019,6 +1019,7 @@ SmiRendezvous (
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BOOLEAN BspInProgress;
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BOOLEAN BspInProgress;
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UINTN Index;
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UINTN Index;
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UINTN Cr2;
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UINTN Cr2;
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BOOLEAN XdDisableFlag;
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//
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//
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// Save Cr2 because Page Fault exception in SMM may override its value
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// Save Cr2 because Page Fault exception in SMM may override its value
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@ -1078,9 +1079,14 @@ SmiRendezvous (
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}
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}
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//
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//
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// Try to enable NX
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// Try to enable XD
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//
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//
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XdDisableFlag = FALSE;
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if (mXdSupported) {
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if (mXdSupported) {
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if ((AsmReadMsr64 (MSR_IA32_MISC_ENABLE) & B_XD_DISABLE_BIT) != 0) {
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XdDisableFlag = TRUE;
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AsmMsrAnd64 (MSR_IA32_MISC_ENABLE, ~B_XD_DISABLE_BIT);
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}
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ActivateXd ();
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ActivateXd ();
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}
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}
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@ -1152,7 +1158,6 @@ SmiRendezvous (
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// BSP Handler is always called with a ValidSmi == TRUE
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// BSP Handler is always called with a ValidSmi == TRUE
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//
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//
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BSPHandler (CpuIndex, mSmmMpSyncData->EffectiveSyncMode);
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BSPHandler (CpuIndex, mSmmMpSyncData->EffectiveSyncMode);
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} else {
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} else {
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APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);
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APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);
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}
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}
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@ -1165,6 +1170,13 @@ SmiRendezvous (
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//
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//
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while (mSmmMpSyncData->AllCpusInSync) {
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while (mSmmMpSyncData->AllCpusInSync) {
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CpuPause ();
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CpuPause ();
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}
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//
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// Restore XD
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//
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if (XdDisableFlag) {
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AsmMsrOr64 (MSR_IA32_MISC_ENABLE, B_XD_DISABLE_BIT);
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}
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}
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}
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}
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@ -21,6 +21,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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/// MSR Register Index
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/// MSR Register Index
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///
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///
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#define MSR_IA32_MISC_ENABLE 0x1A0
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#define MSR_IA32_MISC_ENABLE 0x1A0
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#define B_XD_DISABLE_BIT BIT34
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//
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//
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// External functions
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// External functions
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