mirror of https://github.com/acidanthera/audk.git
OvmfPkg: fold macros of unsupported GPE1 register block into Facp.aslc
In the next patch we're going to specify Extended Addresses of register blocks in Generic Address Structure format. The GAS is easy to fill if we want to posit either "unsupported" (all zero) or a given address in a specific address space. However deriving "unsupported" just from a macro expanding to zero is unwieldy, so let's avoid the need. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14154 6f19259b-4bc3-4df7-8a09-765794883524
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@ -44,14 +44,14 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
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0, // Power Mgt 2 Ctrl Reg Blk unsupported
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PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
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GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
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GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk
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0, // General Purpose Event 1 Reg Blk unsupported
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PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
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PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
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0, // Power Mgt 2 Ctrl Reg Blk unsupported
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PM_TM_LEN, // Byte Length of ports at pm_tm_blk
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GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
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GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
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GPE1_BASE, // offset in gpe model where gpe1 events start
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0, // General Purpose Event 1 Reg Blk unsupported
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0, // General Purpose Event 1 Reg Blk unsupported
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0, // _CST support
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P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
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P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
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@ -38,13 +38,10 @@
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#define PM1a_CNT_BLK 0x0000b004
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#define PM_TMR_BLK 0x0000b008
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#define GPE0_BLK 0x0000afe0
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#define GPE1_BLK 0x00000000
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#define PM1_EVT_LEN 0x04
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#define PM1_CNT_LEN 0x02
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#define PM_TM_LEN 0x04
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#define GPE0_BLK_LEN 0x04
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#define GPE1_BLK_LEN 0x00
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#define GPE1_BASE 0x00
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#define RESERVED 0x00
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#define P_LVL2_LAT 0x0065
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#define P_LVL3_LAT 0x03E9
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