From e21227c62730aa438b8f6e48f81c58a2ddfd6656 Mon Sep 17 00:00:00 2001 From: Olivier Martin Date: Fri, 26 Jul 2013 17:13:08 +0000 Subject: [PATCH] ArmPkg/Library: AArch64 MMU EL1 support Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14508 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c | 31 +++++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c index 2fdfee163a..ae22e86fa9 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c @@ -536,8 +536,10 @@ ArmConfigureMmu ( // // Set TCR that allows us to retrieve T0SZ in the subsequent functions // - if ((ArmReadCurrentEL () == AARCH64_EL2) || (ArmReadCurrentEL () == AARCH64_EL3)) { - //Note: Bits 23 and 31 are reserved bits in TCR_EL2 and TCR_EL3 + // Ideally we will be running at EL2, but should support EL1 as well. + // UEFI should not run at EL3. + if (ArmReadCurrentEL () == AARCH64_EL2) { + //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB; // Set the Physical Address Size using MaxAddress @@ -554,12 +556,33 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) { TCR |= TCR_PS_256TB; } else { - DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU support.\n", MaxAddress)); + DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress)); + ASSERT (0); // Bigger than 48-bit memory space are not supported + return RETURN_UNSUPPORTED; + } + } else if (ArmReadCurrentEL () == AARCH64_EL1) { + TCR = T0SZ | TCR_TG0_4KB; + + // Set the Physical Address Size using MaxAddress + if (MaxAddress < SIZE_4GB) { + TCR |= TCR_IPS_4GB; + } else if (MaxAddress < SIZE_64GB) { + TCR |= TCR_IPS_64GB; + } else if (MaxAddress < SIZE_1TB) { + TCR |= TCR_IPS_1TB; + } else if (MaxAddress < SIZE_4TB) { + TCR |= TCR_IPS_4TB; + } else if (MaxAddress < SIZE_16TB) { + TCR |= TCR_IPS_16TB; + } else if (MaxAddress < SIZE_256TB) { + TCR |= TCR_IPS_256TB; + } else { + DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress)); ASSERT (0); // Bigger than 48-bit memory space are not supported return RETURN_UNSUPPORTED; } } else { - ASSERT (0); // Bigger than 48-bit memory space are not supported + ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3. return RETURN_UNSUPPORTED; }