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UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain 

https://bugzilla.tianocore.org/show_bug.cgi?id=849

In V2, use "mov rax, strict qword 0" to replace the hard code db.

1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Liming Gao 2018-01-11 17:05:15 +08:00
parent 1c7a65eba7
commit e21e355e2c
9 changed files with 79 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
View File

@ -1,7 +1,7 @@
/** @file
Code for Processor S3 restoration
Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -14,6 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include "PiSmmCpuDxeSmm.h"
#pragma pack(1)
typedef struct {
UINTN Lock;
VOID *StackStart;
@ -23,7 +24,9 @@ typedef struct {
IA32_DESCRIPTOR IdtrProfile;
UINT32 BufferStart;
UINT32 Cr3;
UINTN InitializeFloatingPointUnitsAddress;
} MP_CPU_EXCHANGE_INFO;
#pragma pack()
typedef struct {
UINT8 *RendezvousFunnelAddress;
@ -456,6 +459,7 @@ PrepareApStartupVector (
mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
mExchangeInfo->BufferStart = (UINT32) StartupVector;
mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
}
/**

5
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -207,3 +207,6 @@ ASM_PFX(SmiHandler):
ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
ret

6
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -85,3 +85,7 @@ ASM_PFX(SmmRelocationSemaphoreComplete):
mov byte [eax], 1
pop eax
jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
ASM_PFX(PiSmmCpuSmmInitFixupAddress):
ret

8
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@ -1,7 +1,7 @@
/** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
@ -542,6 +542,12 @@ PiCpuSmmEntry (
UINTN ModelId;
UINT32 Cr3;
//
// Initialize address fixup
//
PiSmmCpuSmmInitFixupAddress ();
PiSmmCpuSmiEntryFixupAddress ();
//
// Initialize Debug Agent to support source level debug in SMM code
//

18
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@ -1158,4 +1158,22 @@ EdkiiSmmGetMemoryAttributes (
IN UINT64 *Attributes
);
/**
This function fixes up the address of the global variable or function
referred in SmmInit assembly files to be the absoute address.
**/
VOID
EFIAPI
PiSmmCpuSmmInitFixupAddress (
);
/**
This function fixes up the address of the global variable or function
referred in SmiEntry assembly files to be the absoute address.
**/
VOID
EFIAPI
PiSmmCpuSmiEntryFixupAddress (
);
#endif

9
UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -18,8 +18,6 @@
;
;-------------------------------------------------------------------------------
extern ASM_PFX(InitializeFloatingPointUnits)
%define VacantFlag 0x0
%define NotVacantFlag 0xff
@ -31,6 +29,7 @@ extern ASM_PFX(InitializeFloatingPointUnits)
%define IdtrLocation LockLocation + 0x2A
%define BufferStartLocation LockLocation + 0x34
%define Cr3OffsetLocation LockLocation + 0x38
%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C
;-------------------------------------------------------------------------------------
;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
@ -153,7 +152,7 @@ Releaselock:
;
; Call assembly function to initialize FPU.
;
mov rax, ASM_PFX(InitializeFloatingPointUnits)
mov rax, qword [esi + InitializeFloatingPointUnitsAddress]
sub rsp, 0x20
call rax
add rsp, 0x20
@ -185,7 +184,7 @@ RendezvousFunnelProcEnd:
; comments here for definition of address map
global ASM_PFX(AsmGetAddressMap)
ASM_PFX(AsmGetAddressMap):
mov rax, RendezvousFunnelProcStart
lea rax, [RendezvousFunnelProcStart]
mov qword [rcx], rax
mov qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcStart
mov qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcStart

30
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -158,7 +158,8 @@ Base:
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here
mov rax, ASM_PFX(gSmiHandlerIdtr)
mov rax, strict qword 0 ; mov rax, ASM_PFX(gSmiHandlerIdtr)
SmiHandlerIdtrAbsAddr:
lidt [rax]
lea ebx, [rdi + DSC_OFFSET]
mov ax, [rbx + DSC_DS]
@ -169,7 +170,9 @@ Base:
mov gs, eax
mov ax, [rbx + DSC_SS]
mov ss, eax
; jmp _SmiHandler ; instruction is not needed
mov rax, strict qword 0 ; mov rax, _SmiHandler
_SmiHandlerAbsAddr:
jmp rax
_SmiHandler:
mov rbx, [rsp + 0x8] ; rcx <- CpuIndex
@ -184,16 +187,13 @@ _SmiHandler:
add rsp, -0x20
mov rcx, rbx
mov rax, ASM_PFX(CpuSmmDebugEntry)
call rax
call ASM_PFX(CpuSmmDebugEntry)
mov rcx, rbx
mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRedezvous
call rax
call ASM_PFX(SmiRendezvous)
mov rcx, rbx
mov rax, ASM_PFX(CpuSmmDebugExit)
call rax
call ASM_PFX(CpuSmmDebugExit)
add rsp, 0x20
@ -205,7 +205,7 @@ _SmiHandler:
add rsp, 0x200
mov rax, ASM_PFX(mXdSupported)
lea rax, [ASM_PFX(mXdSupported)]
mov al, [rax]
cmp al, 0
jz .1
@ -222,3 +222,13 @@ _SmiHandler:
ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint
global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
lea rax, [ASM_PFX(gSmiHandlerIdtr)]
lea rcx, [SmiHandlerIdtrAbsAddr]
mov qword [rcx - 8], rax
lea rax, [_SmiHandler]
lea rcx, [_SmiHandlerAbsAddr]
mov qword [rcx - 8], rax
ret

4
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -289,7 +289,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
;; call into exception handler
mov rcx, [rbp + 8]
mov rax, ASM_PFX(SmiPFHandler)
lea rax, [ASM_PFX(SmiPFHandler)]
;; Prepare parameter and call
mov rdx, rsp

17
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
View File

@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@ -60,7 +60,7 @@ ASM_PFX(gSmmCr4): DD 0
ASM_PFX(gSmmCr0): DD 0
mov cr0, rax ; enable protected mode & paging
DB 0x66, 0xea ; far jmp to long mode
ASM_PFX(gSmmJmpAddr): DQ @LongMode
ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
@LongMode: ; long-mode starts here
DB 0x48, 0xbc ; mov rsp, imm64
ASM_PFX(gSmmInitStack): DQ 0
@ -99,7 +99,7 @@ ASM_PFX(gcSmmInitTemplate):
sub ebp, 0x30000
jmp ebp
@L1:
DQ ASM_PFX(SmmStartup)
DQ 0; ASM_PFX(SmmStartup)
ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
@ -128,3 +128,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0
;
db 0xff, 0x25
ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
ASM_PFX(PiSmmCpuSmmInitFixupAddress):
lea rax, [@LongMode]
lea rcx, [ASM_PFX(gSmmJmpAddr)]
mov qword [rcx], rax
lea rax, [ASM_PFX(SmmStartup)]
lea rcx, [@L1]
mov qword [rcx], rax
ret