mirror of https://github.com/acidanthera/audk.git
CorebootPayloadPkg/PlatformHelperLib: Remove unreferenced function
Remove the PlatformFlashEraseWrite function which is not used within CorebootPayloadPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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@ -1,7 +1,7 @@
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/** @file
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PlatformHelperLib function prototype definitions.
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Copyright (c) 2013 Intel Corporation.
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Copyright (c) 2013 - 2016 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -106,42 +106,6 @@ PlatformFlashLockPolicy (
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IN CONST BOOLEAN PreBootPolicy
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);
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/**
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Erase and Write to platform flash.
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Routine accesses one flash block at a time, each access consists
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of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
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of DoErase & DoWrite params must be TRUE.
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Limitations:-
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CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
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DataSize must be a multiple of FLASH_BLOCK_SIZE.
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@param Smst If != NULL then InSmm and use to locate
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SpiProtocol.
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@param CpuWriteAddress Address in CPU memory map of flash region.
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@param Data The buffer containing the data to be written.
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@param DataSize Amount of data to write.
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@param DoErase Earse each block.
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@param DoWrite Write to each block.
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@retval EFI_SUCCESS Operation successful.
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@retval EFI_NOT_READY Required resources not setup.
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@retval EFI_INVALID_PARAMETER Invalid parameter.
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@retval Others Unexpected error happened.
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**/
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EFI_STATUS
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EFIAPI
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PlatformFlashEraseWrite (
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IN VOID *Smst,
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IN UINTN CpuWriteAddress,
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IN UINT8 *Data,
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IN UINTN DataSize,
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IN BOOLEAN DoErase,
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IN BOOLEAN DoWrite
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);
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/** Check if System booted with recovery Boot Stage1 image.
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@retval TRUE If system booted with recovery Boot Stage1 image.
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@ -325,147 +325,6 @@ PlatformFlashLockPolicy (
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}
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}
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/**
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Erase and Write to platform flash.
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Routine accesses one flash block at a time, each access consists
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of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
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of DoErase & DoWrite params must be TRUE.
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Limitations:-
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CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
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DataSize must be a multiple of FLASH_BLOCK_SIZE.
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@param Smst If != NULL then InSmm and use to locate
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SpiProtocol.
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@param CpuWriteAddress Address in CPU memory map of flash region.
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@param Data The buffer containing the data to be written.
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@param DataSize Amount of data to write.
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@param DoErase Earse each block.
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@param DoWrite Write to each block.
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@retval EFI_SUCCESS Operation successful.
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@retval EFI_NOT_READY Required resources not setup.
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@retval EFI_INVALID_PARAMETER Invalid parameter.
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@retval Others Unexpected error happened.
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**/
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EFI_STATUS
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EFIAPI
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PlatformFlashEraseWrite (
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IN VOID *Smst,
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IN UINTN CpuWriteAddress,
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IN UINT8 *Data,
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IN UINTN DataSize,
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IN BOOLEAN DoErase,
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IN BOOLEAN DoWrite
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)
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{
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EFI_STATUS Status;
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UINT64 CpuBaseAddress;
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SPI_INIT_INFO *SpiInfo;
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UINT8 *WriteBuf;
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UINTN Index;
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UINTN SpiWriteAddress;
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EFI_SPI_PROTOCOL *SpiProtocol;
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if (!DoErase && !DoWrite) {
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return EFI_INVALID_PARAMETER;
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}
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if (DoWrite && Data == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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if ((CpuWriteAddress % FLASH_BLOCK_SIZE) != 0) {
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return EFI_INVALID_PARAMETER;
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}
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if ((DataSize % FLASH_BLOCK_SIZE) != 0) {
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return EFI_INVALID_PARAMETER;
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}
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SpiProtocol = LocateSpiProtocol ((EFI_SMM_SYSTEM_TABLE2 *)Smst);
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if (SpiProtocol == NULL) {
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return EFI_NOT_READY;
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}
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//
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// Find info to allow usage of SpiProtocol->Execute.
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//
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Status = SpiProtocol->Info (
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SpiProtocol,
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&SpiInfo
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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ASSERT (SpiInfo->InitTable != NULL);
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ASSERT (SpiInfo->EraseOpcodeIndex < SPI_NUM_OPCODE);
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ASSERT (SpiInfo->ProgramOpcodeIndex < SPI_NUM_OPCODE);
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CpuBaseAddress = PcdGet32 (PcdFlashAreaBaseAddress) - (UINT32)SpiInfo->InitTable->BiosStartOffset;
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ASSERT(CpuBaseAddress >= (SIZE_4GB - SIZE_8MB));
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if (CpuWriteAddress < CpuBaseAddress) {
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return (EFI_INVALID_PARAMETER);
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}
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SpiWriteAddress = CpuWriteAddress - ((UINTN) CpuBaseAddress);
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WriteBuf = Data;
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DEBUG (
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(EFI_D_INFO, "PlatformFlashWrite:SpiWriteAddress=%08x EraseIndex=%d WriteIndex=%d\n",
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SpiWriteAddress,
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(UINTN) SpiInfo->EraseOpcodeIndex,
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(UINTN) SpiInfo->ProgramOpcodeIndex
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));
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for (Index =0; Index < DataSize / FLASH_BLOCK_SIZE; Index++) {
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if (DoErase) {
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DEBUG (
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(EFI_D_INFO, "PlatformFlashWrite:Erase[%04x] SpiWriteAddress=%08x\n",
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Index,
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SpiWriteAddress
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));
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Status = SpiProtocol->Execute (
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SpiProtocol,
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SpiInfo->EraseOpcodeIndex,// OpcodeIndex
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0, // PrefixOpcodeIndex
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FALSE, // DataCycle
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TRUE, // Atomic
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FALSE, // ShiftOut
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SpiWriteAddress, // Address
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0, // Data Number
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NULL,
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EnumSpiRegionAll // SPI_REGION_TYPE
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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}
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if (DoWrite) {
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DEBUG (
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(EFI_D_INFO, "PlatformFlashWrite:Write[%04x] SpiWriteAddress=%08x\n",
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Index,
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SpiWriteAddress
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));
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Status = SpiProtocol->Execute (
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SpiProtocol,
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SpiInfo->ProgramOpcodeIndex, // OpcodeIndex
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0, // PrefixOpcodeIndex
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TRUE, // DataCycle
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TRUE, // Atomic
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TRUE, // ShiftOut
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SpiWriteAddress, // Address
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FLASH_BLOCK_SIZE, // Data Number
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WriteBuf,
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EnumSpiRegionAll
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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WriteBuf+=FLASH_BLOCK_SIZE;
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}
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SpiWriteAddress+=FLASH_BLOCK_SIZE;
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}
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return EFI_SUCCESS;
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}
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/** Check if System booted with recovery Boot Stage1 image.
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@retval TRUE If system booted with recovery Boot Stage1 image.
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