UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

UefiCpuPkg/Include/Register/Msr/Core2Msr.h

@@ -41,6 +41,7 @@
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
   @endcode
+  @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
 **/
 #define MSR_CORE2_PLATFORM_ID                    0x00000017
 
@@ -89,6 +90,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
   AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 **/
 #define MSR_CORE2_EBL_CR_POWERON                 0x0000002A
 
@@ -202,6 +204,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
   AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
 **/
 #define MSR_CORE2_FEATURE_CONTROL                0x0000003A
 
@@ -253,6 +256,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
   @{
 **/
 #define MSR_CORE2_LASTBRANCH_0_FROM_IP           0x00000040
@@ -279,6 +286,10 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
   @{
 **/
 #define MSR_CORE2_LASTBRANCH_0_TO_IP             0x00000060
@@ -306,6 +317,7 @@ typedef union {
   Msr.Uint64 = 0;
   AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
 **/
 #define MSR_CORE2_SMRR_PHYSBASE                  0x000000A0
 
@@ -353,6 +365,7 @@ typedef union {
   Msr.Uint64 = 0;
   AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
 **/
 #define MSR_CORE2_SMRR_PHYSMASK                  0x000000A1
 
@@ -402,6 +415,7 @@ typedef union {
 
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
   @endcode
+  @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 **/
 #define MSR_CORE2_FSB_FREQ                       0x000000CD
 
@@ -460,6 +474,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
   AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 **/
 #define MSR_CORE2_BBL_CR_CTL3                    0x0000011E
 
@@ -518,6 +533,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
   AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 **/
 #define MSR_CORE2_PERF_STATUS                    0x00000198
 
@@ -577,6 +593,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
   AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 **/
 #define MSR_CORE2_THERM2_CTL                     0x0000019D
 
@@ -628,6 +645,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
   AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 **/
 #define MSR_CORE2_IA32_MISC_ENABLE               0x000001A0
 
@@ -795,6 +813,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
   AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
   @endcode
+  @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 **/
 #define MSR_CORE2_LASTBRANCH_TOS                 0x000001C9
 
@@ -814,6 +833,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
   @endcode
+  @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 **/
 #define MSR_CORE2_LER_FROM_LIP                   0x000001DD
 
@@ -834,6 +854,7 @@ typedef union {
 
   Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
   @endcode
+  @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 **/
 #define MSR_CORE2_LER_TO_LIP                     0x000001DE
 
@@ -852,6 +873,9 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
   AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
   @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
   @{
 **/
 #define MSR_CORE2_PERF_FIXED_CTR0                0x00000309
@@ -877,6 +901,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
   AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
 **/
 #define MSR_CORE2_PERF_CAPABILITIES              0x00000345
 
@@ -928,6 +953,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
   AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
   @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
 **/
 #define MSR_CORE2_PERF_FIXED_CTR_CTRL            0x0000038D
 
@@ -947,6 +973,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_CORE2_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_CORE2_IA32_PERF_GLOBAL_STAUS         0x0000038E
 
@@ -965,6 +992,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);
   AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);
   @endcode
+  @note MSR_CORE2_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.
 **/
 #define MSR_CORE2_PERF_GLOBAL_STAUS              0x0000038E
 
@@ -983,6 +1011,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
   AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
   @endcode
+  @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
 **/
 #define MSR_CORE2_PERF_GLOBAL_CTRL               0x0000038F
 
@@ -1001,6 +1030,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
   AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
   @endcode
+  @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
 **/
 #define MSR_CORE2_PERF_GLOBAL_OVF_CTRL           0x00000390
 
@@ -1022,6 +1052,7 @@ typedef union {
   Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
   AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
   @endcode
+  @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 **/
 #define MSR_CORE2_PEBS_ENABLE                    0x000003F1
 
@@ -1065,6 +1096,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);
   AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);
   @endcode
+  @note MSR_CORE2_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 **/
 #define MSR_CORE2_MC4_CTL                        0x0000040C
 
@@ -1083,6 +1115,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
 **/
 #define MSR_CORE2_MC4_STATUS                     0x0000040D
 
@@ -1105,6 +1138,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);
   AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);
   @endcode
+  @note MSR_CORE2_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
 **/
 #define MSR_CORE2_MC4_ADDR                       0x0000040E
 
@@ -1123,6 +1157,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);
   AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);
   @endcode
+  @note MSR_CORE2_MC3_CTL is defined as MSR_MC3_CTL in SDM.
 **/
 #define MSR_CORE2_MC3_CTL                        0x00000410
 
@@ -1141,6 +1176,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
 **/
 #define MSR_CORE2_MC3_STATUS                     0x00000411
 
@@ -1163,6 +1199,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);
   AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);
   @endcode
+  @note MSR_CORE2_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
 **/
 #define MSR_CORE2_MC3_ADDR                       0x00000412
 
@@ -1181,6 +1218,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);
   AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);
   @endcode
+  @note MSR_CORE2_MC3_MISC is defined as MSR_MC3_MISC in SDM.
 **/
 #define MSR_CORE2_MC3_MISC                       0x00000413
 
@@ -1199,6 +1237,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);
   AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);
   @endcode
+  @note MSR_CORE2_MC5_CTL is defined as MSR_MC5_CTL in SDM.
 **/
 #define MSR_CORE2_MC5_CTL                        0x00000414
 
@@ -1217,6 +1256,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
 **/
 #define MSR_CORE2_MC5_STATUS                     0x00000415
 
@@ -1235,6 +1275,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);
   AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);
   @endcode
+  @note MSR_CORE2_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
 **/
 #define MSR_CORE2_MC5_ADDR                       0x00000416
 
@@ -1253,6 +1294,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);
   AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);
   @endcode
+  @note MSR_CORE2_MC5_MISC is defined as MSR_MC5_MISC in SDM.
 **/
 #define MSR_CORE2_MC5_MISC                       0x00000417
 
@@ -1272,6 +1314,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);
   AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);
   @endcode
+  @note MSR_CORE2_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
 **/
 #define MSR_CORE2_MC6_STATUS                     0x00000419
 
@@ -1291,6 +1334,14 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
   AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
   @endcode
+  @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
   @{
 **/
 #define MSR_CORE2_EMON_L3_CTR_CTL0               0x000107CC
@@ -1319,6 +1370,7 @@ typedef union {
   Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
   AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
   @endcode
+  @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
 **/
 #define MSR_CORE2_EMON_L3_GL_CTL                 0x000107D8