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UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265

Support collecting cache associative type in CpuCacheInfoLib.
This prevents the user from using additional code to obtain the
same information.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
This commit is contained in:
Lou, Yun 2021-03-15 21:48:53 +08:00 committed by mergify[bot]
parent 2e51b27fed
commit e4ff3773b7
3 changed files with 53 additions and 26 deletions
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15
UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
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@ -1,7 +1,7 @@
/** @file
Header file for CPU Cache info Library.
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -33,7 +33,18 @@ typedef struct {
// Ways of associativity.
// Value = CPUID.04h:EBX[31:22]
//
UINT16 CacheWays;
UINT16 CacheWays : 10;
//
// Fully associative cache.
// Value = CPUID.04h:EAX[09]
//
UINT16 FullyAssociativeCache : 1;
//
// Direct mapped cache.
// Value = CPUID.04h:EDX[02]
//
UINT16 DirectMappedCache : 1;
UINT16 Reserved : 4;
//
// Size of single cache that this package's this type of logical processor corresponds to.
// Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *

49
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
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@ -1,7 +1,7 @@
/** @file
Provides cache info for each package, core type, cache level and cache type.
Copyright (c) 2020 Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -23,18 +23,18 @@ CpuCacheInfoPrintCpuCacheInfoTable (
{
UINTN Index;
DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));
DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays CacheSizeinKB CacheCount |\n"));
DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays (FA|DM) CacheSizeinKB CacheCount |\n"));
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
for (Index = 0; Index < CpuCacheInfoCount; Index++) {
DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x %8x %4x |\n", Index,
CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,
CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].CacheSizeinKB,
CpuCacheInfo[Index].CacheCount));
DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,
CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache,
CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount));
}
DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------------------------------+\n"));
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
}
/**
@ -160,6 +160,7 @@ CpuCacheInfoCollectCoreAndCacheData (
CPUID_CACHE_PARAMS_EAX CacheParamEax;
CPUID_CACHE_PARAMS_EBX CacheParamEbx;
UINT32 CacheParamEcx;
CPUID_CACHE_PARAMS_EDX CacheParamEdx;
CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;
COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;
CPUID_CACHE_DATA *CacheData;
@ -185,17 +186,19 @@ CpuCacheInfoCollectCoreAndCacheData (
CacheParamLeafIndex = 0;
while (CacheParamLeafIndex < MAX_NUM_OF_CACHE_PARAMS_LEAF) {
AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, NULL);
AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, &CacheParamEdx.Uint32);
if (CacheParamEax.Bits.CacheType == 0) {
break;
}
CacheData[CacheParamLeafIndex].CacheLevel = (UINT8)CacheParamEax.Bits.CacheLevel;
CacheData[CacheParamLeafIndex].CacheType = (UINT8)CacheParamEax.Bits.CacheType;
CacheData[CacheParamLeafIndex].CacheWays = (UINT16)CacheParamEbx.Bits.Ways;
CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) *
CacheData[CacheParamLeafIndex].CacheLevel = (UINT8)CacheParamEax.Bits.CacheLevel;
CacheData[CacheParamLeafIndex].CacheType = (UINT8)CacheParamEax.Bits.CacheType;
CacheData[CacheParamLeafIndex].CacheWays = (UINT16)CacheParamEbx.Bits.Ways;
CacheData[CacheParamLeafIndex].FullyAssociativeCache = (UINT8)CacheParamEax.Bits.FullyAssociativeCache;
CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)CacheParamEdx.Bits.ComplexCacheIndexing;
CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) *
(CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;
CacheParamLeafIndex++;
@ -305,13 +308,15 @@ CpuCacheInfoCollectCpuCacheInfoData (
if (CacheInfoIndex == LocalCacheInfoCount) {
ASSERT (LocalCacheInfoCount < MaxCacheInfoCount);
LocalCacheInfo[LocalCacheInfoCount].Package = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;
LocalCacheInfo[LocalCacheInfoCount].CoreType = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;
LocalCacheInfo[LocalCacheInfoCount].CacheLevel = CacheData[Index].CacheLevel;
LocalCacheInfo[LocalCacheInfoCount].CacheType = CacheData[Index].CacheType;
LocalCacheInfo[LocalCacheInfoCount].CacheWays = CacheData[Index].CacheWays;
LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB = CacheData[Index].CacheSizeinKB;
LocalCacheInfo[LocalCacheInfoCount].CacheCount = 1;
LocalCacheInfo[LocalCacheInfoCount].Package = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;
LocalCacheInfo[LocalCacheInfoCount].CoreType = ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;
LocalCacheInfo[LocalCacheInfoCount].CacheLevel = CacheData[Index].CacheLevel;
LocalCacheInfo[LocalCacheInfoCount].CacheType = CacheData[Index].CacheType;
LocalCacheInfo[LocalCacheInfoCount].CacheWays = CacheData[Index].CacheWays;
LocalCacheInfo[LocalCacheInfoCount].FullyAssociativeCache = CacheData[Index].FullyAssociativeCache;
LocalCacheInfo[LocalCacheInfoCount].DirectMappedCache = CacheData[Index].DirectMappedCache;
LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB = CacheData[Index].CacheSizeinKB;
LocalCacheInfo[LocalCacheInfoCount].CacheCount = 1;
LocalCacheInfoCount++;
}

15
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
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@ -1,7 +1,7 @@
/** @file
Internal header file for CPU Cache info Library.
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -52,7 +52,18 @@ typedef struct {
// Ways of associativity.
// Value = CPUID.04h:EBX[31:22]
//
UINT16 CacheWays;
UINT16 CacheWays : 10;
//
// Fully associative cache.
// Value = CPUID.04h:EAX[09]
//
UINT16 FullyAssociativeCache : 1;
//
// Direct mapped cache.
// Value = CPUID.04h:EDX[02]
//
UINT16 DirectMappedCache : 1;
UINT16 Reserved : 4;
//
// Cache share bits.
// Value = CPUID.04h:EAX[25:14]