mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PlatformPei: Refactor InitializeRamRegions
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 InitializeRamRegions is refactored into 3 calls: - PlatformQemuInitializeRam - SevInitializeRam - PlatformQemuInitializeRamForS3 SevInitializeRam is not in PlatformInitLib. Because in the first stage PlatformInitLib only support the basic platform featues. PlatformQemuInitializeRamForS3 wraps the code which was previously in InitializeRamRegions (many code in 2 if-checks). Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
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@ -161,7 +161,7 @@ PlatformQemuUc32BaseInitialization (
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// variable MTRR suffices by truncating the size to a whole power of two,
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// while keeping the end affixed to 4GB. This will round the base up.
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//
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LowerMemorySize = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
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LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
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PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));
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PlatformInfoHob->Uc32Base = (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32Size);
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//
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@ -372,7 +372,8 @@ GetHighestSystemMemoryAddressFromPvhMemmap (
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}
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UINT32
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GetSystemMemorySizeBelow4gb (
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EFIAPI
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PlatformGetSystemMemorySizeBelow4gb (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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@ -761,7 +762,7 @@ PublishPeiMemory (
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UINT32 S3AcpiReservedMemoryBase;
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UINT32 S3AcpiReservedMemorySize;
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LowerMemorySize = GetSystemMemorySizeBelow4gb (&mPlatformInfoHob);
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LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (&mPlatformInfoHob);
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if (mPlatformInfoHob.SmmSmramRequire) {
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//
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// TSEG is chipped from the end of low RAM
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@ -871,7 +872,7 @@ QemuInitializeRamBelow1gb (
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**/
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STATIC
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VOID
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QemuInitializeRam (
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PlatformQemuInitializeRam (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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@ -885,7 +886,7 @@ QemuInitializeRam (
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//
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// Determine total memory size available
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//
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LowerMemorySize = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
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LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
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if (PlatformInfoHob->BootMode == BOOT_ON_S3_RESUME) {
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//
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@ -995,19 +996,12 @@ QemuInitializeRam (
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}
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}
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/**
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Publish system RAM and reserve memory regions
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**/
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STATIC
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VOID
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InitializeRamRegions (
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PlatformQemuInitializeRamForS3 (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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QemuInitializeRam (PlatformInfoHob);
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SevInitializeRam ();
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if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME)) {
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//
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// This is the memory range that will be used for PEI on S3 resume
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@ -1113,7 +1107,7 @@ InitializeRamRegions (
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//
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TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;
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BuildMemoryAllocationHob (
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GetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize,
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PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize,
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TsegSize,
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EfiReservedMemoryType
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);
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@ -1152,3 +1146,19 @@ InitializeRamRegions (
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#endif
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}
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}
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/**
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Publish system RAM and reserve memory regions
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**/
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VOID
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InitializeRamRegions (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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)
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{
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PlatformQemuInitializeRam (PlatformInfoHob);
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SevInitializeRam ();
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PlatformQemuInitializeRamForS3 (PlatformInfoHob);
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}
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@ -79,7 +79,7 @@ MemMapInitialization (
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return;
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}
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TopOfLowRam = GetSystemMemorySizeBelow4gb (PlatformInfoHob);
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TopOfLowRam = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);
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PciExBarBase = 0;
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if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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@ -35,7 +35,8 @@ PublishPeiMemory (
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);
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UINT32
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GetSystemMemorySizeBelow4gb (
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EFIAPI
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PlatformGetSystemMemorySizeBelow4gb (
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IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob
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);
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