IntelFsp2WrapperPkg: Support UPD allocation outside FspWrapper

UPD allocation and patching can be done outside FspWrapper
as implementation choice so adding a PCD to select between
original FspWrapper allocation model or outside model

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Chasel, Chiu 2017-11-23 10:22:45 +08:00
parent 984ba6a467
commit e69dcef54e
5 changed files with 76 additions and 52 deletions

View File

@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -63,20 +63,29 @@ PeiFspMemoryInit (
DEBUG ((DEBUG_INFO, "PeiFspMemoryInit enter\n"));
FspHobListPtr = NULL;
FspmUpdDataPtr = NULL;
//
// Copy default FSP-M UPD data from Flash
//
FspmHeaderPtr = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));
DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
if (FspmHeaderPtr == NULL) {
return EFI_DEVICE_ERROR;
}
if (PcdGet32 (PcdFspmUpdDataAddress) == 0 && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) {
//
// Copy default FSP-M UPD data from Flash
//
FspmUpdDataPtr = (FSPM_UPD_COMMON *)AllocateZeroPool ((UINTN)FspmHeaderPtr->CfgRegionSize);
ASSERT (FspmUpdDataPtr != NULL);
SourceData = (UINTN *)((UINTN)FspmHeaderPtr->ImageBase + (UINTN)FspmHeaderPtr->CfgRegionOffset);
CopyMem (FspmUpdDataPtr, SourceData, (UINTN)FspmHeaderPtr->CfgRegionSize);
} else {
//
// External UPD is ready, get the buffer from PCD pointer.
//
FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress);
ASSERT (FspmUpdDataPtr != NULL);
}
DEBUG ((DEBUG_INFO, "UpdateFspmUpdData enter\n"));
UpdateFspmUpdData ((VOID *)FspmUpdDataPtr);

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@ -60,6 +60,7 @@
[Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES
[Sources]
FspmWrapperPeim.c

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@ -3,7 +3,7 @@
register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -234,22 +234,27 @@ PeiMemoryDiscoveredNotify (
FSPS_UPD_COMMON *FspsUpdDataPtr;
UINTN *SourceData;
DEBUG ((DEBUG_INFO, "PeiMemoryDiscoveredNotify enter\n"));
FspsUpdDataPtr = NULL;
//
// Copy default FSP-S UPD data from Flash
//
FspsHeaderPtr = (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFspsBaseAddress));
DEBUG ((DEBUG_INFO, "FspsHeaderPtr - 0x%x\n", FspsHeaderPtr));
if (FspsHeaderPtr == NULL) {
return EFI_DEVICE_ERROR;
}
if (PcdGet32 (PcdFspsUpdDataAddress) == 0 && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
//
// Copy default FSP-S UPD data from Flash
//
FspsUpdDataPtr = (FSPS_UPD_COMMON *)AllocateZeroPool ((UINTN)FspsHeaderPtr->CfgRegionSize);
ASSERT (FspsUpdDataPtr != NULL);
SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
} else {
FspsUpdDataPtr = (FSPS_UPD_COMMON *)PcdGet32 (PcdFspsUpdDataAddress);
ASSERT (FspsUpdDataPtr != NULL);
}
UpdateFspsUpdData ((VOID *)FspsUpdDataPtr);
@ -342,7 +347,6 @@ FspsWrapperPeimEntryPoint (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n"));
FspsWrapperInit ();

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@ -67,6 +67,7 @@
[Pcd]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
[Guids]
gFspHobGuid ## CONSUMES ## HOB

View File

@ -1,7 +1,7 @@
## @file
# Provides drivers and definitions to support fsp in EDKII bios.
#
# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
@ -95,4 +95,13 @@
[PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx]
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x00001001
#
# To provide flexibility for platform to pre-allocate FSP UPD buffer
#
# The PCDs define the pre-allocated FSPM and FSPS UPD Data Buffer Address.
# 0x00000000 - Platform will not pre-allocate UPD buffer before FspWrapper module
# non-zero - Platform will pre-allocate UPD buffer and patch this value to
# buffer address before FspWrapper module executing.
#
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000
gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001