mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmGic: Introduced helper functions to access the GIC controller
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15621 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
oliviermartin
parent
4edcf21de4
commit
e700a1fc91
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@ -2,7 +2,7 @@
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Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
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Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
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Portions copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -14,7 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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Gic.c
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ArmGicDxe.c
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Abstract:
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@ -111,20 +111,12 @@ EnableInterruptSource (
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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// Write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
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ArmGicEnableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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@ -146,20 +138,12 @@ DisableInterruptSource (
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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// Calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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// Write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
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ArmGicDisableInterrupt (PcdGet32(PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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@ -183,23 +167,12 @@ GetInterruptSourceState (
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IN BOOLEAN *InterruptState
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)
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{
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UINT32 RegOffset;
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UINTN RegShift;
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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// calculate enable register offset and bit position
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RegOffset = Source / 32;
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RegShift = Source % 32;
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if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
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*InterruptState = FALSE;
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} else {
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*InterruptState = TRUE;
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}
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*InterruptState = ArmGicIsInterruptEnabled (PcdGet32(PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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@ -315,11 +288,10 @@ ExitBootServicesEvent (
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}
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// Disable Gic Interface
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
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ArmGicDisableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// Disable Gic Distributor
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
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ArmGicDisableDistributor (PcdGet32(PcdGicDistributorBase));
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}
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/**
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@ -393,10 +365,10 @@ InterruptDxeInitialize (
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
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// Enable gic cpu interface
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
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ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// Enable gic distributor
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
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ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
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// Initialize the array for the Interrupt Handlers
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gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -57,7 +57,7 @@
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#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
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#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
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#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
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#define ARM_GIC_ICCIDR 0xFC // Identification Register
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#define ARM_GIC_ICCIIDR 0xFC // Identification Register
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#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
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#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
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@ -71,14 +71,20 @@
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#define ARM_GIC_ICCICR_USE_SBPR 0x10
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// Bit Mask for GICC_IIDR
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#define ARM_GIC_ICCIDR_GET_PRODUCT_ID(IccIdr) (((IccIdr) >> 20) & 0xFFF)
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#define ARM_GIC_ICCIDR_GET_ARCH_VERSION(IccIdr) (((IccIdr) >> 16) & 0xF)
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#define ARM_GIC_ICCIDR_GET_REVISION(IccIdr) (((IccIdr) >> 12) & 0xF)
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#define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr) ((IccIdr) & 0xFFF)
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#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
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#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
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#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
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#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
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// Bit Mask for
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#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
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UINTN
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EFIAPI
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ArmGicGetInterfaceIdentification (
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IN INTN GicInterruptInterfaceBase
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);
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//
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// GIC Secure interfaces
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//
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@ -116,6 +122,12 @@ ArmGicEnableDistributor (
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IN INTN GicDistributorBase
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);
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VOID
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EFIAPI
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ArmGicDisableDistributor (
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IN INTN GicDistributorBase
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);
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UINTN
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EFIAPI
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ArmGicGetMaxNumInterrupts (
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@ -151,4 +163,25 @@ ArmGicSetPriorityMask (
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IN INTN PriorityMask
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);
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VOID
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EFIAPI
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ArmGicEnableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN Source
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);
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VOID
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EFIAPI
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ArmGicDisableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN Source
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);
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BOOLEAN
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EFIAPI
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ArmGicIsInterruptEnabled (
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IN UINTN GicDistributorBase,
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IN UINTN Source
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);
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#endif
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -73,10 +73,10 @@ ArmPlatformSecInitialize (
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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// Read the GIC Identification Register
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Identification = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIDR);
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Identification = ArmGicGetInterfaceIdentification (PcdGet32 (PcdGicInterruptInterfaceBase));
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// Check if we are GICv3
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if (ARM_GIC_ICCIDR_GET_ARCH_VERSION(Identification) >= 0x3) {
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if (ARM_GIC_ICCIIDR_GET_ARCH_VERSION(Identification) >= 0x3) {
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InitializeGicV3 ();
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}
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