tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from IA32 SmmStartup() 

The SmmStartup() executes in SMM, which is very similar to real mode. Add
"BITS 16" before it and "BITS 32" after it (just before the @32bit label).

Remove the manual 0x66 operand-size override prefixes, for selecting
32-bit operands -- the sizes of our operands trigger NASM to insert the
prefixes automatically in almost every spot. The one place where we have
to add it back manually is the LGDT instruction. (The 0x67 address-size
override prefix is also auto-generated.)

This patch causes NASM to generate byte-identical object code (determined
by disassembling both the pre-patch and post-patch versions, and comparing
the listings), except:

> @@ -158,7 +158,7 @@
>  00000142  6689D3            mov ebx,edx
>  00000145  66B800000000      mov eax,0x0
>  0000014B  0F22D8            mov cr3,eax
> -0000014E  67662E0F0155F6    o32 lgdt [cs:ebp-0xa]
> +0000014E  2E66670F0155F6    o32 lgdt [cs:ebp-0xa]
>  00000155  66B800000000      mov eax,0x0
>  0000015B  0F22E0            mov cr4,eax
>  0000015E  66B9800000C0      mov ecx,0xc0000080

The only difference is the prefix list order, it changes from:

- 0x67, 0x66, 0x2E

to

- 0x2E, 0x66, 0x67

(0x2E is "CS segment override").

Cc: Eric Dong <eric.dong@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This commit is contained in:
Laszlo Ersek 2018-01-30 14:43:28 +01:00
parent 994df20926
commit e75ee97224
1 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
View File

@ -41,24 +41,21 @@ ASM_PFX(gcSmiInitGdtr):
DQ 0 DQ 0
global ASM_PFX(SmmStartup) global ASM_PFX(SmmStartup)
BITS 16
ASM_PFX(SmmStartup): ASM_PFX(SmmStartup):
DB 0x66
mov eax, 0x80000001 ; read capability mov eax, 0x80000001 ; read capability
cpuid cpuid
DB 0x66
mov ebx, edx ; rdmsr will change edx. keep it in ebx. mov ebx, edx ; rdmsr will change edx. keep it in ebx.
DB 0x66, 0xb8 ; mov eax, imm32 DB 0x66, 0xb8 ; mov eax, imm32
ASM_PFX(gSmmCr3): DD 0 ASM_PFX(gSmmCr3): DD 0
mov cr3, eax mov cr3, eax
DB 0x67, 0x66 o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
DB 0x66, 0xb8 ; mov eax, imm32 DB 0x66, 0xb8 ; mov eax, imm32
ASM_PFX(gSmmCr4): DD 0 ASM_PFX(gSmmCr4): DD 0
mov cr4, eax mov cr4, eax
DB 0x66
mov ecx, 0xc0000080 ; IA32_EFER MSR mov ecx, 0xc0000080 ; IA32_EFER MSR
rdmsr rdmsr
DB 0x66
test ebx, BIT20 ; check NXE capability test ebx, BIT20 ; check NXE capability
jz .1 jz .1
or ah, BIT3 ; set NXE bit or ah, BIT3 ; set NXE bit
@ -66,12 +63,14 @@ ASM_PFX(gSmmCr4): DD 0
.1: .1:
DB 0x66, 0xb8 ; mov eax, imm32 DB 0x66, 0xb8 ; mov eax, imm32
ASM_PFX(gSmmCr0): DD 0 ASM_PFX(gSmmCr0): DD 0
DB 0xbf, PROTECT_MODE_DS, 0 ; mov di, PROTECT_MODE_DS mov di, PROTECT_MODE_DS
mov cr0, eax mov cr0, eax
DB 0x66, 0xea ; jmp far [ptr48] DB 0x66, 0xea ; jmp far [ptr48]
ASM_PFX(gSmmJmpAddr): ASM_PFX(gSmmJmpAddr):
DD @32bit DD @32bit
DW PROTECT_MODE_CS DW PROTECT_MODE_CS
BITS 32
@32bit: @32bit:
mov ds, edi mov ds, edi
mov es, edi mov es, edi