mirror of https://github.com/acidanthera/audk.git
UefiPayloadPkg: Add a common SMM control Runtime DXE module
This module consumes SMM Registers HOB (SMI_GBL_EN and SMI_APM_EN) to install SMM control 2 protocol gEfiSmmControl2ProtocolGuid. The protocol activate() would set SMI_GBL_EN and SMI_APM_EN and trigger SMI by writing to IO port 0xB3 and 0xB2. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com>
This commit is contained in:
Guo Dong
mergify[bot]
parent
87a34ca0cf
commit
e7e8ea27d4
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@ -0,0 +1,48 @@
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/** @file
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This file defines the SMM info hob structure.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef PAYLOAD_SMM_REGISTER_INFO_GUID_H_
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#define PAYLOAD_SMM_REGISTER_INFO_GUID_H_
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#include <IndustryStandard/Acpi.h>
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///
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/// SMM Information GUID
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///
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extern EFI_GUID gSmmRegisterInfoGuid;
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///
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/// Reuse ACPI definition
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/// AddressSpaceId(0xC0-0xFF) is defined by OEM for MSR and other spaces
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///
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typedef EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE PLD_GENERIC_ADDRESS;
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#define REGISTER_ID_SMI_GBL_EN 1
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#define REGISTER_ID_SMI_GBL_EN_LOCK 2
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#define REGISTER_ID_SMI_EOS 3
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#define REGISTER_ID_SMI_APM_EN 4
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#define REGISTER_ID_SMI_APM_STS 5
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#pragma pack(1)
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typedef struct {
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UINT64 Id;
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UINT64 Value;
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PLD_GENERIC_ADDRESS Address;
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} PLD_GENERIC_REGISTER;
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typedef struct {
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UINT16 Revision;
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UINT16 Reserved;
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UINT32 Count;
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PLD_GENERIC_REGISTER Registers[0];
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} PLD_SMM_REGISTERS;
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#pragma pack()
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#endif
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@ -0,0 +1,256 @@
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/** @file
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This module produces the SMM Control2 Protocol
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PiDxe.h>
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#include <Protocol/SmmControl2.h>
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#include <Library/DebugLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/UefiRuntimeLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Guid/SmmRegisterInfoGuid.h>
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#define SMM_DATA_PORT 0xB3
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#define SMM_CONTROL_PORT 0xB2
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typedef struct {
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UINT8 GblBitOffset;
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UINT8 ApmBitOffset;
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UINT32 Address;
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} SMM_CONTROL2_REG;
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SMM_CONTROL2_REG mSmiCtrlReg;
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/**
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Invokes SMI activation from either the preboot or runtime environment.
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This function generates an SMI.
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@param[in] This The EFI_SMM_CONTROL2_PROTOCOL instance.
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@param[in,out] CommandPort The value written to the command port.
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@param[in,out] DataPort The value written to the data port.
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@param[in] Periodic Optional mechanism to engender a periodic stream.
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@param[in] ActivationInterval Optional parameter to repeat at this period one
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time or, if the Periodic Boolean is set, periodically.
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@retval EFI_SUCCESS The SMI has been engendered.
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@retval EFI_DEVICE_ERROR The timing is unsupported.
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@retval EFI_INVALID_PARAMETER The activation period is unsupported.
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@retval EFI_INVALID_PARAMETER The last periodic activation has not been cleared.
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@retval EFI_NOT_STARTED The MM base service has not been initialized.
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**/
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EFI_STATUS
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EFIAPI
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Activate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN OUT UINT8 *CommandPort OPTIONAL,
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IN OUT UINT8 *DataPort OPTIONAL,
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IN BOOLEAN Periodic OPTIONAL,
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IN EFI_SMM_PERIOD ActivationInterval OPTIONAL
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)
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{
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UINT32 SmiEn;
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UINT32 SmiEnableBits;
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if (Periodic) {
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return EFI_INVALID_PARAMETER;
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}
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SmiEn = IoRead32 (mSmiCtrlReg.Address);
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SmiEnableBits = (1 << mSmiCtrlReg.GblBitOffset) | (1 << mSmiCtrlReg.ApmBitOffset);
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if ((SmiEn & SmiEnableBits) != SmiEnableBits) {
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//
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// Set the "global SMI enable" bit and APM bit
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//
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IoWrite32 (mSmiCtrlReg.Address, SmiEn | SmiEnableBits);
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}
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IoWrite8 (SMM_DATA_PORT, DataPort == NULL ? 0 : *DataPort);
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IoWrite8 (SMM_CONTROL_PORT, CommandPort == NULL ? 0 : *CommandPort);
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return EFI_SUCCESS;
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}
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/**
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Clears an SMI.
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@param This Pointer to an instance of EFI_SMM_CONTROL2_PROTOCOL
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@param Periodic TRUE to indicate a periodical SMI
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@return Return value from SmmClear ()
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**/
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EFI_STATUS
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EFIAPI
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Deactivate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN BOOLEAN Periodic
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)
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{
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if (Periodic) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Temporarily do nothing here
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//
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return EFI_SUCCESS;
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}
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///
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/// SMM COntrol2 Protocol instance
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///
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EFI_SMM_CONTROL2_PROTOCOL mSmmControl2 = {
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Activate,
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Deactivate,
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0
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};
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/**
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Get specified SMI register based on given register ID
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@param[in] SmmRegister SMI related register array from bootloader
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@param[in] Id The register ID to get.
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@retval NULL The register is not found or the format is not expected.
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@return smi register
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**/
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PLD_GENERIC_REGISTER *
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GetSmmCtrlRegById (
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IN PLD_SMM_REGISTERS *SmmRegister,
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IN UINT32 Id
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)
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{
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UINT32 Index;
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PLD_GENERIC_REGISTER *PldReg;
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PldReg = NULL;
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for (Index = 0; Index < SmmRegister->Count; Index++) {
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if (SmmRegister->Registers[Index].Id == Id) {
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PldReg = &SmmRegister->Registers[Index];
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break;
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}
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}
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if (PldReg == NULL) {
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DEBUG ((DEBUG_INFO, "Register %d not found.\n", Id));
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return NULL;
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}
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//
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// Checking the register if it is expected.
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//
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if ((PldReg->Address.AccessSize != EFI_ACPI_3_0_DWORD) ||
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(PldReg->Address.Address == 0) ||
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(PldReg->Address.RegisterBitWidth != 1) ||
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(PldReg->Address.AddressSpaceId != EFI_ACPI_3_0_SYSTEM_IO) ||
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(PldReg->Value != 1)) {
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DEBUG ((DEBUG_INFO, "Unexpected SMM register.\n"));
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DEBUG ((DEBUG_INFO, "AddressSpaceId= 0x%x\n", PldReg->Address.AddressSpaceId));
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DEBUG ((DEBUG_INFO, "RegBitWidth = 0x%x\n", PldReg->Address.RegisterBitWidth));
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DEBUG ((DEBUG_INFO, "RegBitOffset = 0x%x\n", PldReg->Address.RegisterBitOffset));
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DEBUG ((DEBUG_INFO, "AccessSize = 0x%x\n", PldReg->Address.AccessSize));
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DEBUG ((DEBUG_INFO, "Address = 0x%lx\n",PldReg->Address.Address ));
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return NULL;
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}
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return PldReg;
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}
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/**
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Fixup data pointers so that the services can be called in virtual mode.
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@param[in] Event The event registered.
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@param[in] Context Event context.
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**/
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VOID
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EFIAPI
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SmmControlVirtualAddressChangeEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EfiConvertPointer (0x0, (VOID **) &(mSmmControl2.Trigger));
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EfiConvertPointer (0x0, (VOID **) &(mSmmControl2.Clear));
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}
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/**
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This function installs EFI_SMM_CONTROL2_PROTOCOL.
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@param ImageHandle Handle for the image of this driver
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@param SystemTable Pointer to the EFI System Table
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@retval EFI_UNSUPPORTED There's no Intel ICH on this platform
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@return The status returned from InstallProtocolInterface().
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**/
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EFI_STATUS
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EFIAPI
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SmmControlEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_HOB_GUID_TYPE *GuidHob;
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PLD_SMM_REGISTERS *SmmRegister;
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PLD_GENERIC_REGISTER *SmiGblEnReg;
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PLD_GENERIC_REGISTER *SmiApmEnReg;
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EFI_EVENT Event;
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GuidHob = GetFirstGuidHob (&gSmmRegisterInfoGuid);
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if (GuidHob == NULL) {
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return EFI_UNSUPPORTED;
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}
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SmmRegister = (PLD_SMM_REGISTERS *) (GET_GUID_HOB_DATA(GuidHob));
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SmiGblEnReg = GetSmmCtrlRegById (SmmRegister, REGISTER_ID_SMI_GBL_EN);
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if (SmiGblEnReg == NULL) {
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DEBUG ((DEBUG_ERROR, "SMI global enable reg not found.\n"));
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return EFI_NOT_FOUND;
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}
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mSmiCtrlReg.Address = (UINT32)SmiGblEnReg->Address.Address;
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mSmiCtrlReg.GblBitOffset = SmiGblEnReg->Address.RegisterBitOffset;
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SmiApmEnReg = GetSmmCtrlRegById (SmmRegister, REGISTER_ID_SMI_APM_EN);
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if (SmiApmEnReg == NULL) {
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DEBUG ((DEBUG_ERROR, "SMI APM enable reg not found.\n"));
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return EFI_NOT_FOUND;
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}
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if (SmiApmEnReg->Address.Address != mSmiCtrlReg.Address) {
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DEBUG ((DEBUG_ERROR, "SMI APM EN and SMI GBL EN are expected to have same register base\n"));
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DEBUG ((DEBUG_ERROR, "APM:0x%x, GBL:0x%x\n", SmiApmEnReg->Address.Address, mSmiCtrlReg.Address));
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return EFI_UNSUPPORTED;
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}
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mSmiCtrlReg.ApmBitOffset = SmiApmEnReg->Address.RegisterBitOffset;
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//
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// Install our protocol interfaces on the device's handle
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//
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Status = gBS->InstallMultipleProtocolInterfaces (
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&ImageHandle,
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&gEfiSmmControl2ProtocolGuid,
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&mSmmControl2,
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NULL
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);
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ASSERT_EFI_ERROR (Status);
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_NOTIFY,
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SmmControlVirtualAddressChangeEvent,
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NULL,
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&gEfiEventVirtualAddressChangeGuid,
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&Event
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);
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return Status;
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}
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@ -0,0 +1,50 @@
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## @file
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# SMM Control runtime DXE Module
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#
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# Provides the ability to generate a software SMI.
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#
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# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = SmmControlRuntimeDxe
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FILE_GUID = C3099578-F815-4a96-84A3-FC593760181D
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MODULE_TYPE = DXE_RUNTIME_DRIVER
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VERSION_STRING = 1.0
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ENTRY_POINT = SmmControlEntryPoint
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = IA32 X64
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#
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[Sources]
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SmmControlRuntimeDxe.c
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[Packages]
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MdePkg/MdePkg.dec
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UefiPayloadPkg/UefiPayloadPkg.dec
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[LibraryClasses]
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UefiDriverEntryPoint
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DebugLib
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UefiBootServicesTableLib
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UefiRuntimeLib
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PcdLib
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IoLib
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HobLib
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[Guids]
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gSmmRegisterInfoGuid
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gEfiEventVirtualAddressChangeGuid
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[Protocols]
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gEfiSmmControl2ProtocolGuid ## PRODUCES
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[Depex]
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TRUE
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@ -37,6 +37,8 @@
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gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }
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gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }
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gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }
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gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }
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gSmmRegisterInfoGuid = { 0xaa9bd7a7, 0xcafb, 0x4499, { 0xa4, 0xa9, 0xb, 0x34, 0x6b, 0x40, 0xa6, 0x22 } }
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[Ppis]
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[Ppis]
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gEfiPayLoadHobBasePpiGuid = { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }
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gEfiPayLoadHobBasePpiGuid = { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }
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