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IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.Limit

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According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.

"Bits N:0 of the limit register are
decoded by hardware as all 1s."

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Star Zeng 2018-01-16 16:41:42 +08:00
parent 6478baf891
commit e8097a74b7
1 changed files with 3 additions and 3 deletions
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6
IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c
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@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License which accompanies this distribution. the terms and conditions of the BSD License which accompanies this distribution.
@ -60,7 +60,7 @@ typedef struct {
PEI Memory Layout: PEI Memory Layout:
+------------------+ <=============== PHMR.Limit (Top of memory) +------------------+ <=============== PHMR.Limit (+ alignment) (Top of memory)
| Mem Resource | | Mem Resource |
| | | |
@ -72,7 +72,7 @@ typedef struct {
DMA Buffer | * DMA FREE * | DMA Buffer | * DMA FREE * |
| | -------------- | | | -------------- |
V | Read/Write Buf | V | Read/Write Buf |
=========== +==================+ <=============== PLMR.Limit =========== +==================+ <=============== PLMR.Limit (+ alignment)
| PEI allocated | | PEI allocated |
| -------------- | <------- EfiFreeMemoryTop | -------------- | <------- EfiFreeMemoryTop
| * PEI FREE * | | * PEI FREE * |