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Make sure FIQ debugger stuff can work. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10369 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-04-13 22:30:42 +00:00
parent 9d1d7243f0
commit e9fc14b6e1
3 changed files with 11 additions and 2 deletions
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2
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -86,7 +86,6 @@ ArmCleanDataCacheEntryBySetWay
ArmInvalidateInstructionCache ArmInvalidateInstructionCache
mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
dsb
isb isb
bx LR bx LR
@ -228,3 +227,4 @@ ArmInstructionSynchronizationBarrier
bx LR bx LR
END END

1
Omap35xxPkg/Include/Omap3530/Omap3530Interrupt.h
View File

@ -39,6 +39,7 @@
#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n))) #define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m))) #define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
#define INTCPS_ILR_FIQ BIT0
#define INTCPS_SIR_IRQ_MASK (0x7F) #define INTCPS_SIR_IRQ_MASK (0x7F)
#define INTCPS_CONTROL_NEWIRQAGR BIT0 #define INTCPS_CONTROL_NEWIRQAGR BIT0
#define INTCPS_CONTROL_NEWFIQAGR BIT1 #define INTCPS_CONTROL_NEWFIQAGR BIT1

8
Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
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@ -87,6 +87,14 @@ RegisterInterruptSource (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {
// This vector has been programmed as FIQ so we can't use it for IRQ
// EFI does not use FIQ, but the debugger can use it to check for
// ctrl-c. So this ASSERT means you have a conflict with the debug agent
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) { if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }