mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
The timer compare register is 64-bit so simplifying the delay function. Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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@ -20,6 +20,5 @@
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Name:
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Name:
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#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
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#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
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#define RISCV_TIMER_COMPARE_BITS 32
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#endif
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#endif
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@ -22,26 +22,19 @@
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@param Delay A period of time to delay in ticks.
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@param Delay A period of time to delay in ticks.
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**/
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**/
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STATIC
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VOID
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VOID
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InternalRiscVTimerDelay (
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InternalRiscVTimerDelay (
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IN UINT32 Delay
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IN UINT64 Delay
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)
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)
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{
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{
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UINT32 Ticks;
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UINT64 Ticks;
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UINT32 Times;
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Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
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Ticks = RiscVReadTimer () + Delay;
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Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
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do {
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while (RiscVReadTimer () <= Ticks) {
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//
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CpuPause ();
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// The target timer count is calculated here
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}
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//
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Ticks = RiscVReadTimer () + Delay;
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Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
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while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
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CpuPause ();
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}
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} while (Times-- > 0);
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}
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}
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/**
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/**
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@ -61,13 +54,13 @@ MicroSecondDelay (
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)
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)
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{
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{
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InternalRiscVTimerDelay (
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InternalRiscVTimerDelay (
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(UINT32)DivU64x32 (
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DivU64x32 (
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MultU64x32 (
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MultU64x32 (
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MicroSeconds,
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MicroSeconds,
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PcdGet64 (PcdCpuCoreCrystalClockFrequency)
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PcdGet64 (PcdCpuCoreCrystalClockFrequency)
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),
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),
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1000000u
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1000000u
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)
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)
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);
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);
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return MicroSeconds;
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return MicroSeconds;
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}
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}
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@ -89,13 +82,13 @@ NanoSecondDelay (
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)
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)
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{
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{
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InternalRiscVTimerDelay (
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InternalRiscVTimerDelay (
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(UINT32)DivU64x32 (
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DivU64x32 (
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MultU64x32 (
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MultU64x32 (
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NanoSeconds,
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NanoSeconds,
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PcdGet64 (PcdCpuCoreCrystalClockFrequency)
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PcdGet64 (PcdCpuCoreCrystalClockFrequency)
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),
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),
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1000000000u
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1000000000u
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)
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)
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);
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);
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return NanoSeconds;
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return NanoSeconds;
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}
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}
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