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UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit 

The timer compare register is 64-bit so simplifying the delay
function.

Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
This commit is contained in:
Tuan Phan 2023-06-07 10:30:21 -07:00 committed by mergify[bot]
parent 4dba2a9d08
commit ea55bd8f66
2 changed files with 22 additions and 30 deletions
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1
MdePkg/Include/Register/RiscV64/RiscVImpl.h
View File

@ -20,6 +20,5 @@
Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define RISCV_TIMER_COMPARE_BITS 32
#endif

51
UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
View File

@ -22,26 +22,19 @@
@param Delay A period of time to delay in ticks.
**/
STATIC
VOID
InternalRiscVTimerDelay (
IN UINT32 Delay
IN UINT64 Delay
)
{
UINT32 Ticks;
UINT32 Times;
UINT64 Ticks;
Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
do {
//
// The target timer count is calculated here
//
Ticks = RiscVReadTimer () + Delay;
Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
CpuPause ();
}
} while (Times-- > 0);
Ticks = RiscVReadTimer () + Delay;
while (RiscVReadTimer () <= Ticks) {
CpuPause ();
}
}
/**
@ -61,13 +54,13 @@ MicroSecondDelay (
)
{
InternalRiscVTimerDelay (
(UINT32)DivU64x32 (
MultU64x32 (
MicroSeconds,
PcdGet64 (PcdCpuCoreCrystalClockFrequency)
),
1000000u
)
DivU64x32 (
MultU64x32 (
MicroSeconds,
PcdGet64 (PcdCpuCoreCrystalClockFrequency)
),
1000000u
)
);
return MicroSeconds;
}
@ -89,13 +82,13 @@ NanoSecondDelay (
)
{
InternalRiscVTimerDelay (
(UINT32)DivU64x32 (
MultU64x32 (
NanoSeconds,
PcdGet64 (PcdCpuCoreCrystalClockFrequency)
),
1000000000u
)
DivU64x32 (
MultU64x32 (
NanoSeconds,
PcdGet64 (PcdCpuCoreCrystalClockFrequency)
),
1000000000u
)
);
return NanoSeconds;
}