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ArmPkg/ArmGic: Retire ArmGicArchLib

Browse Source 
ArmGicArchLib is no longer use so remove all remaining references and
implementations.

Continuous-integration-options: PatchCheck.ignore-multi-package

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel 2025-01-16 18:31:09 +01:00 committed by mergify[bot]
parent 34ab9197a5
commit eaa60a6b10
9 changed files with 0 additions and 206 deletions
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5
ArmPkg/ArmPkg.dec
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@ -36,11 +36,6 @@
#
ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
## @libraryclass Provides an interface to initialize a
# Generic Interrupt Controller (GIC).
#
ArmGicArchLib|Include/Library/ArmGicArchLib.h
## @libraryclass Provides a Generic Interrupt Controller (GIC)
# configuration interface.
#

3
ArmPkg/ArmPkg.dsc
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@ -68,7 +68,6 @@
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
ArmSvcLib|ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
@ -154,8 +153,6 @@
ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
ArmPkg/Library/ArmLib/ArmBaseLib.inf
ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf
ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf

1
ArmPkg/Drivers/ArmGic/ArmGicLib.inf
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@ -23,7 +23,6 @@
ArmLib
DebugLib
IoLib
ArmGicArchLib
[Packages]
ArmPkg/ArmPkg.dec

40
ArmPkg/Include/Library/ArmGicArchLib.h
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@ -1,40 +0,0 @@
/** @file
*
* Copyright (c) 2015, Linaro Ltd. All rights reserved.
* Copyright (c) 2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
* @par Reference(s):
* - Arm Generic Interrupt Controller Architecture Specification,
* Issue H, January 2022.
* (https://developer.arm.com/documentation/ihi0069/)
*
**/
#ifndef ARM_GIC_ARCH_LIB_H_
#define ARM_GIC_ARCH_LIB_H_
//
// GIC definitions
//
typedef enum {
ARM_GIC_ARCH_REVISION_2,
ARM_GIC_ARCH_REVISION_3
} ARM_GIC_ARCH_REVISION;
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
VOID
);
//
// GIC SPI and extended SPI ranges
//
#define ARM_GIC_ARCH_SPI_MIN 32
#define ARM_GIC_ARCH_SPI_MAX 1019
#define ARM_GIC_ARCH_EXT_SPI_MIN 4096
#define ARM_GIC_ARCH_EXT_SPI_MAX 5119
#endif // ARM_GIC_ARCH_LIB_H_

61
ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c
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@ -1,61 +0,0 @@
/** @file
*
* Copyright (c) 2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
RETURN_STATUS
EFIAPI
ArmGicArchLibInitialize (
VOID
)
{
UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
// get it wrong. It is more reliable to check if the GICv3 System Register
// feature is implemented on the CPU. This is also convenient as our GICv3
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmHasGicSystemRegisters ()) {
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need
// to fall back to the GICv2 MMIO interface.
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
if (!(IccSre & ICC_SRE_EL2_SRE)) {
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
if (IccSre & ICC_SRE_EL2_SRE) {
mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
goto Done;
}
}
mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
Done:
return RETURN_SUCCESS;
}
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
VOID
)
{
return mGicArchRevision;
}

25
ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
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@ -1,25 +0,0 @@
#/* @file
# Copyright (c) 2015, Linaro Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmGicArchLib
FILE_GUID = cd67f41a-26e9-4482-90c9-a9aff803382a
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmGicArchLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION
CONSTRUCTOR = ArmGicArchLibInitialize
[Sources]
ArmGicArchLib.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
ArmGicLib

46
ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c
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@ -1,46 +0,0 @@
/** @file
*
* Copyright (c) 2014, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
VOID
)
{
UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
// get it wrong. It is more reliable to check if the GICv3 System Register
// feature is implemented on the CPU. This is also convenient as our GICv3
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmHasGicSystemRegisters ()) {
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need
// to fall back to the GICv2 MMIO interface.
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
if (!(IccSre & ICC_SRE_EL2_SRE)) {
ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
}
return ARM_GIC_ARCH_REVISION_2;
}

24
ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
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@ -1,24 +0,0 @@
#/* @file
# Copyright (c) 2015, Linaro Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmGicArchSecLib
FILE_GUID = c1dd9745-9459-4e9a-9f5b-99cbd233c27d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmGicArchLib|SEC
[Sources]
ArmGicArchLib.c
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
ArmGicLib

1
ArmPlatformPkg/ArmPlatformPkg.dsc
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@ -36,7 +36,6 @@
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
ArmPlatformLib|ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf