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ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers when Uniprocessor 

When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero).
So the previous assertion was not correct.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2013-10-24 11:49:32 +00:00 committed by oliviermartin
parent d62f9aa6e6
commit eb5c268fb6
1 changed files with 6 additions and 6 deletions
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6
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
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@ -378,13 +378,13 @@ InterruptDxeInitialize (
CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR); CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
// cannot be 0. // is 0 when we run on a uniprocessor platform.
ASSERT (CpuTarget != 0); if (CpuTarget != 0) {
// The 8 first Interrupt Processor Targets Registers are read-only // The 8 first Interrupt Processor Targets Registers are read-only
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) { for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget); MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
} }
}
// Set binary point reg to 0x7 (no preemption) // Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);