mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpuDxeSmm: Consume SMM Base Hob for SmBase info
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337 Existing SMBASE Relocation is in the PiSmmCpuDxeSmm driver, which will relocate the SMBASE of each processor by setting the SMBASE field in the saved state map (at offset 7EF8h) to a new value. The RSM instruction reloads the internal SMBASE register with the value in SMBASE field when each time it exits SMM. All subsequent SMI requests will use the new SMBASE to find the starting address for the SMI handler (at SMBASE + 8000h). Due to the default SMBASE for all x86 processors is 0x30000, the APs' 1st SMI for rebase has to be executed one by one to avoid the processors over-writing each other's SMM Save State Area (see existing SmmRelocateBases() function), which means the next AP has to wait for the previous AP to finish its 1st SMI, then it can call into its 1st SMI for rebase via Smi Ipi command, thus leading the existing SMBASE Relocation has to be running in series. Besides, it needs very complex code to handle the AP exit semaphore (mRebased[Index]), which will hook return address of SMM Save State so that semaphore code can be executed immediately after AP exits SMM for SMBASE relocation (see existing SemaphoreHook() function). With SMM Base Hob support, PiSmmCpuDxeSmm does not need the RSM instruction to do the SMBASE Relocation. SMBASE Register for each processors have already been programmed and all SMBASE address have recorded in SMM Base Hob. So the same default SMBASE Address (0x30000) will not be used, thus the processors over-writing each other's SMM Save State Area will not happen in PiSmmCpuDxeSmm driver. This way makes the first SMI init can be executed in parallel and save boot time on multi-core system. Besides, Semaphore Hook code logic is also not required, which will greatly simplify the SMBASE Relocation flow. Mainly changes as below: * Assume the biggest possibility of tile size is 8k. * Combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate) into one (gcSmiHandlerTemplate), the new SMI handler needs to run to 2 paths: one to SmmCpuFeaturesInitializeProcessor(), the other to SMM Core Entry Point. * Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for first SMI init before normal SMI sources happen. * Call SmmCpuFeaturesInitializeProcessor() in parallel. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Wu, Jiaxin
mergify[bot]
parent
7b8c5a8eb4
commit
ec07fd0e35
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@ -1,7 +1,7 @@
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/** @file
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Code for Processor S3 restoration
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Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -824,9 +824,34 @@ SmmRestoreCpu (
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}
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//
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// Restore SMBASE for BSP and all APs
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// Make sure the gSmmBaseHobGuid existence status is the same between normal and S3 boot.
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//
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SmmRelocateBases ();
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ASSERT (mSmmRelocated == (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) != NULL));
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if (mSmmRelocated != (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) != NULL)) {
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DEBUG ((
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DEBUG_ERROR,
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"gSmmBaseHobGuid %a produced in normal boot but %a in S3 boot!",
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mSmmRelocated ? "is" : "is not",
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mSmmRelocated ? "is not" : "is"
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));
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CpuDeadLoop ();
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}
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//
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// Check whether Smm Relocation is done or not.
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// If not, will do the SmmBases Relocation here!!!
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//
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if (!mSmmRelocated) {
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//
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// Restore SMBASE for BSP and all APs
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//
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SmmRelocateBases ();
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} else {
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//
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// Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init.
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//
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ExecuteFirstSmiInit ();
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}
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//
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// Skip initialization if mAcpiCpuData is not valid
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@ -1,7 +1,7 @@
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/** @file
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SMM MP service implementation
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Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -1723,6 +1723,10 @@ SmiRendezvous (
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ASSERT (CpuIndex < mMaxNumberOfCpus);
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if (mSmmRelocated) {
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ASSERT (mSmmInitialized != NULL);
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}
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//
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// Save Cr2 because Page Fault exception in SMM may override its value,
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// when using on-demand paging for above 4G memory.
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@ -1730,6 +1734,25 @@ SmiRendezvous (
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Cr2 = 0;
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SaveCr2 (&Cr2);
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if (mSmmRelocated && !mSmmInitialized[CpuIndex]) {
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//
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// Perform SmmInitHandler for CpuIndex
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//
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SmmInitHandler ();
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//
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// Restore Cr2
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//
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RestoreCr2 (Cr2);
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//
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// Mark the first SMI init for CpuIndex has been done so as to avoid the reentry.
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//
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mSmmInitialized[CpuIndex] = TRUE;
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return;
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}
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//
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// Call the user register Startup function first.
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//
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@ -84,6 +84,8 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {
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EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
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BOOLEAN mSmmRelocated = FALSE;
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volatile BOOLEAN *mSmmInitialized = NULL;
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UINT32 mBspApicId = 0;
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//
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@ -383,10 +385,12 @@ SmmInitHandler (
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InitializeMpSyncData ();
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}
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//
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// Hook return after RSM to set SMM re-based flag
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//
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SemaphoreHook (Index, &mRebased[Index]);
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if (!mSmmRelocated) {
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//
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// Hook return after RSM to set SMM re-based flag
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//
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SemaphoreHook (Index, &mRebased[Index]);
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}
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return;
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}
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@ -395,6 +399,51 @@ SmmInitHandler (
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ASSERT (FALSE);
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}
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/**
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Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init.
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**/
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VOID
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ExecuteFirstSmiInit (
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VOID
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)
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{
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UINTN Index;
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if (mSmmInitialized == NULL) {
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mSmmInitialized = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * mMaxNumberOfCpus);
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}
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ASSERT (mSmmInitialized != NULL);
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if (mSmmInitialized == NULL) {
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return;
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}
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//
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// Reset the mSmmInitialized to false.
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//
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ZeroMem ((VOID *)mSmmInitialized, sizeof (BOOLEAN) * mMaxNumberOfCpus);
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//
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// Get the BSP ApicId.
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//
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mBspApicId = GetApicId ();
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//
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// Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) for SMM init
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//
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SendSmiIpi (mBspApicId);
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SendSmiIpiAllExcludingSelf ();
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//
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// Wait for all processors to finish its 1st SMI
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//
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for (Index = 0; Index < mNumberOfCpus; Index++) {
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while (!(BOOLEAN)mSmmInitialized[Index]) {
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}
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}
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}
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/**
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Relocate SmmBases for each processor.
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@ -562,6 +611,11 @@ PiCpuSmmEntry (
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UINTN FamilyId;
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UINTN ModelId;
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UINT32 Cr3;
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EFI_HOB_GUID_TYPE *GuidHob;
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SMM_BASE_HOB_DATA *SmmBaseHobData;
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GuidHob = NULL;
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SmmBaseHobData = NULL;
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//
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// Initialize address fixup
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@ -790,26 +844,54 @@ PiCpuSmmEntry (
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ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
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//
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// Allocate buffer for all of the tiles.
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// Retrive the allocated SmmBase from gSmmBaseHobGuid. If found,
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// means the SmBase relocation has been done.
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 34.11 SMBASE Relocation
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// For Pentium and Intel486 processors, the SMBASE values must be
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// aligned on a 32-KByte boundary or the processor will enter shutdown
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// state during the execution of a RSM instruction.
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//
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// Intel486 processors: FamilyId is 4
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// Pentium processors : FamilyId is 5
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//
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BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));
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if ((FamilyId == 4) || (FamilyId == 5)) {
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Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);
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} else {
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Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
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}
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GuidHob = GetFirstGuidHob (&gSmmBaseHobGuid);
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if (GuidHob != NULL) {
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//
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// Check whether the Required TileSize is enough.
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//
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if (TileSize > SIZE_8KB) {
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DEBUG ((DEBUG_ERROR, "The Range of Smbase in SMRAM is not enough -- Required TileSize = 0x%08x, Actual TileSize = 0x%08x\n", TileSize, SIZE_8KB));
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CpuDeadLoop ();
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return RETURN_BUFFER_TOO_SMALL;
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}
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ASSERT (Buffer != NULL);
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DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));
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SmmBaseHobData = GET_GUID_HOB_DATA (GuidHob);
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//
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// Assume single instance of HOB produced, expect the HOB.NumberOfProcessors equals to the mMaxNumberOfCpus.
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//
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ASSERT (SmmBaseHobData->NumberOfProcessors == (UINT32)mMaxNumberOfCpus && SmmBaseHobData->ProcessorIndex == 0);
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mSmmRelocated = TRUE;
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} else {
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//
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// When the HOB doesn't exist, allocate new SMBASE itself.
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//
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DEBUG ((DEBUG_INFO, "PiCpuSmmEntry: gSmmBaseHobGuid not found!\n"));
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//
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// Allocate buffer for all of the tiles.
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//
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// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
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// Volume 3C, Section 34.11 SMBASE Relocation
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// For Pentium and Intel486 processors, the SMBASE values must be
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// aligned on a 32-KByte boundary or the processor will enter shutdown
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// state during the execution of a RSM instruction.
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//
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// Intel486 processors: FamilyId is 4
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// Pentium processors : FamilyId is 5
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//
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BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));
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if ((FamilyId == 4) || (FamilyId == 5)) {
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Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);
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} else {
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Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
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}
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ASSERT (Buffer != NULL);
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DEBUG ((DEBUG_INFO, "New Allcoated SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));
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}
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//
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// Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
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@ -844,7 +926,8 @@ PiCpuSmmEntry (
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// size for each CPU in the platform
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//
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for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
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mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
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mCpuHotPlugData.SmBase[Index] = mSmmRelocated ? (UINTN)SmmBaseHobData->SmBase[Index] : (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
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gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP);
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gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
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gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
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@ -957,17 +1040,23 @@ PiCpuSmmEntry (
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InitializeSmmIdt ();
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//
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// Relocate SMM Base addresses to the ones allocated from SMRAM
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// Check whether Smm Relocation is done or not.
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// If not, will do the SmmBases Relocation here!!!
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//
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mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);
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ASSERT (mRebased != NULL);
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SmmRelocateBases ();
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if (!mSmmRelocated) {
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//
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// Relocate SMM Base addresses to the ones allocated from SMRAM
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//
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mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);
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ASSERT (mRebased != NULL);
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SmmRelocateBases ();
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//
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// Call hook for BSP to perform extra actions in normal mode after all
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// SMM base addresses have been relocated on all CPUs
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//
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SmmCpuFeaturesSmmRelocationComplete ();
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//
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// Call hook for BSP to perform extra actions in normal mode after all
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// SMM base addresses have been relocated on all CPUs
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//
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SmmCpuFeaturesSmmRelocationComplete ();
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}
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DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported));
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@ -998,6 +1087,21 @@ PiCpuSmmEntry (
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}
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}
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//
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// For relocated SMBASE, some MSRs & CSRs are still required to be configured in SMM Mode for SMM Initialization.
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// Those MSRs & CSRs must be configured before normal SMI sources happen.
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// So, here is to issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init.
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//
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if (mSmmRelocated) {
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ExecuteFirstSmiInit ();
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//
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// Call hook for BSP to perform extra actions in normal mode after all
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// SMM base addresses have been relocated on all CPUs
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//
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SmmCpuFeaturesSmmRelocationComplete ();
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}
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//
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// Fill in SMM Reserved Regions
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//
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@ -1,7 +1,7 @@
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/** @file
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Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
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Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -25,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
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#include <Guid/AcpiS3Context.h>
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#include <Guid/MemoryAttributesTable.h>
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#include <Guid/PiSmmMemoryAttributesTable.h>
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#include <Guid/SmmBaseHob.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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@ -348,6 +349,25 @@ SmmWriteSaveState (
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IN CONST VOID *Buffer
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);
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/**
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C function for SMI handler. To change all processor's SMMBase Register.
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**/
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VOID
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EFIAPI
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SmmInitHandler (
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VOID
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);
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/**
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Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init.
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**/
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VOID
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ExecuteFirstSmiInit (
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VOID
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);
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/**
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Read a CPU Save State register on the target processor.
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@ -402,6 +422,10 @@ WriteSaveStateRegister (
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IN CONST VOID *Buffer
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);
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extern BOOLEAN mSmmRelocated;
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extern volatile BOOLEAN *mSmmInitialized;
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extern UINT32 mBspApicId;
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extern CONST UINT8 gcSmmInitTemplate[];
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extern CONST UINT16 gcSmmInitSize;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;
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@ -4,7 +4,7 @@
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# This SMM driver performs SMM initialization, deploy SMM Entry Vector,
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# provides CPU specific services in SMM.
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#
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# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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@ -114,6 +114,7 @@
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gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # it is used for S3 boot.
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gEdkiiPiSmmMemoryAttributesTableGuid ## CONSUMES ## SystemTable
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gEfiMemoryAttributesTableGuid ## CONSUMES ## SystemTable
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gSmmBaseHobGuid ## CONSUMES
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[FeaturePcd]
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONSUMES
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