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IntelFrameworkModulePkg/FwVolDxe: Ensure FfsFileHeader 8 bytes aligned
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=864 REF: CVE-2018-3630 To follow PI spec, ensure FfsFileHeader 8 bytes aligned. Current code only handles (FwVolHeader->ExtHeaderOffset != 0) path, update code to also handle (FwVolHeader->ExtHeaderOffset == 0) path. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
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@ -4,7 +4,7 @@
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Layers on top of Firmware Block protocol to produce a file abstraction
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Layers on top of Firmware Block protocol to produce a file abstraction
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of FV based files.
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of FV based files.
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions
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are licensed and made available under the terms and conditions
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@ -510,10 +510,10 @@ FvCheck (
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//
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//
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FwVolExtHeader = (EFI_FIRMWARE_VOLUME_EXT_HEADER *) (UINTN) (FvDevice->CachedFv + FvDevice->FwVolHeader->ExtHeaderOffset);
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FwVolExtHeader = (EFI_FIRMWARE_VOLUME_EXT_HEADER *) (UINTN) (FvDevice->CachedFv + FvDevice->FwVolHeader->ExtHeaderOffset);
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Ptr = (UINT8 *) FwVolExtHeader + FwVolExtHeader->ExtHeaderSize;
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Ptr = (UINT8 *) FwVolExtHeader + FwVolExtHeader->ExtHeaderSize;
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Ptr = (UINT8 *) ALIGN_POINTER (Ptr, 8);
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} else {
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} else {
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Ptr = (UINT8 *) (UINTN) (FvDevice->CachedFv + FvDevice->FwVolHeader->HeaderLength);
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Ptr = (UINT8 *) (UINTN) (FvDevice->CachedFv + FvDevice->FwVolHeader->HeaderLength);
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}
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}
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Ptr = (UINT8 *) ALIGN_POINTER (Ptr, 8);
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TopFvAddress = (UINT8 *) (UINTN) (FvDevice->CachedFv + FvDevice->FwVolHeader->FvLength);
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TopFvAddress = (UINT8 *) (UINTN) (FvDevice->CachedFv + FvDevice->FwVolHeader->FvLength);
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//
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//
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