mirror of https://github.com/acidanthera/audk.git
SecurityPkg:Tcg2Smm:Enabling TPM SIRQ interrupt support
1. Report TPM SIRQ interrupt resource through _CRS 2. Expose _SRS to update interrupt resource & FIFO/TIS interrupt related registers defined in TCG PC Client Platform TPM Profile (PTP) Specification spec https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2-0-v43-150126.pdf Note: IHV/OEM need to carefully verify this feature with OS TPM driver to make sure there is no impact to system/HW Cc: Long Qin <qin.long@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Long Qin <qin.long@intel.com>
This commit is contained in:
Zhang, Chao B
parent
3c12f346a1
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@ -43,13 +43,6 @@ DefinitionBlock (
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//
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Name (_STR, Unicode ("TPM 2.0 Device"))
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//
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// Return the resource consumed by TPM device
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//
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Name (_CRS, ResourceTemplate () {
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Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
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})
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//
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// Operational region for Smi port access
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//
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@ -65,7 +58,19 @@ DefinitionBlock (
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OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)
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Field (TPMR, AnyAcc, NoLock, Preserve)
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{
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ACC0, 8,
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ACC0, 8, // TPM_ACCESS_0
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Offset(0x8),
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INTE, 32, // TPM_INT_ENABLE_0
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INTV, 8, // TPM_INT_VECTOR_0
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Offset(0x10),
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INTS, 32, // TPM_INT_STATUS_0
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INTF, 32, // TPM_INTF_CAPABILITY_0
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STS0, 32, // TPM_STS_0
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Offset(0x24),
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FIFO, 32, // TPM_DATA_FIFO_0
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Offset(0x30),
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TID0, 32, // TPM_INTERFACE_ID_0
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// ignore the rest
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}
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//
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@ -89,6 +94,97 @@ DefinitionBlock (
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UCRQ, 32 // Phyical Presence request operation to Get User Confirmation Status
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}
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Name(RESO, ResourceTemplate () {
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Memory32Fixed (ReadWrite, 0xfed40000, 0x5000, REGS)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) {12}
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})
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//
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// Return the resource consumed by TPM device.
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//
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Method(_CRS,0,Serialized)
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{
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Return(RESO)
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}
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//
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// Set resources consumed by the TPM device. This is used to
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// assign an interrupt number to the device. The input byte stream
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// has to be the same as returned by _CRS (according to ACPI spec).
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//
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Method(_SRS,1,Serialized)
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{
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//
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// Update resource descriptor
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// Use the field name to identify the offsets in the argument
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// buffer and RESO buffer.
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//
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CreateDWordField(Arg0, ^IRQ._INT, IRQ0)
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CreateDWordField(RESO, ^IRQ._INT, LIRQ)
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Store(IRQ0, LIRQ)
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CreateBitField(Arg0, ^IRQ._HE, ITRG)
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CreateBitField(RESO, ^IRQ._HE, LTRG)
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Store(ITRG, LTRG)
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CreateBitField(Arg0, ^IRQ._LL, ILVL)
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CreateBitField(RESO, ^IRQ._LL, LLVL)
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Store(ILVL, LLVL)
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//
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// Update TPM FIFO PTP/TIS interface only, identified by TPM_INTERFACE_ID_x lowest
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// nibble.
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// 0000 - FIFO interface as defined in PTP for TPM 2.0 is active
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// 1111 - FIFO interface as defined in TIS1.3 is active
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//
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If (LOr(LEqual (And (TID0, 0x0F), 0x00), LEqual (And (TID0, 0x0F), 0x0F))) {
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//
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// If FIFO interface, interrupt vector register is
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// available. TCG PTP specification allows only
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// values 1..15 in this field. For other interrupts
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// the field should stay 0.
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//
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If (LLess (IRQ0, 16)) {
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Store (And(IRQ0, 0xF), INTV)
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}
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//
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// Interrupt enable register (TPM_INT_ENABLE_x) bits 3:4
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// contains settings for interrupt polarity.
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// The other bits of the byte enable individual interrupts.
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// They should be all be zero, but to avoid changing the
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// configuration, the other bits are be preserved.
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// 00 - high level
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// 01 - low level
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// 10 - rising edge
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// 11 - falling edge
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//
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// ACPI spec definitions:
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// _HE: '1' is Edge, '0' is Level
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// _LL: '1' is ActiveHigh, '0' is ActiveLow (inverted from TCG spec)
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//
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If (LEqual (ITRG, 1)) {
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Or(INTE, 0x00000010, INTE)
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} Else {
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And(INTE, 0xFFFFFFEF, INTE)
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}
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if (LEqual (ILVL, 0)) {
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Or(INTE, 0x00000008, INTE)
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} Else {
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And(INTE, 0xFFFFFFF7, INTE)
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}
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}
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}
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//
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// Possible resource settings.
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// The format of the data has to follow the same format as
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// _CRS (according to ACPI spec).
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//
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Name (_PRS, ResourceTemplate() {
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Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , SIRQ) {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}
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})
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Method (PTS, 1, Serialized)
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{
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//
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