mirror of https://github.com/acidanthera/audk.git
Cleanup to match MdePkg cleanups. More progress on ARM disassembler.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9924 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
parent
334f978ecc
commit
eeb78924ec
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@ -28,6 +28,7 @@
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#include <Library/UefiLib.h>
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#include <Library/CpuLib.h>
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#include <Library/DefaultExceptionHandlerLib.h>
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#include <Library/DebugLib.h>
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#include <Guid/DebugImageInfoTable.h>
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#include <Protocol/Cpu.h>
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@ -57,6 +57,7 @@
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UefiLib
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CpuLib
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DefaultExceptioHandlerLib
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DebugLib
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[Protocols]
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gEfiCpuArchProtocolGuid
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@ -22,6 +22,7 @@
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#include <Base.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PrintLib.h>
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extern CHAR8 *gCondition[];
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@ -30,6 +31,8 @@ extern CHAR8 *gReg[];
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// Thumb address modes
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#define LOAD_STORE_FORMAT1 1
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#define LOAD_STORE_FORMAT1_H 101
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#define LOAD_STORE_FORMAT1_B 111
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#define LOAD_STORE_FORMAT2 2
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#define LOAD_STORE_FORMAT3 3
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#define LOAD_STORE_FORMAT4 4
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@ -74,9 +77,10 @@ extern CHAR8 *gReg[];
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#define SRS_FORMAT 215
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#define RFE_FORMAT 216
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#define LDRD_REG_IMM8_SIGNED 217
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#define ADD_IMM12 218
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#define ADD_IMM5 219
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#define ADR_THUMB2 220
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#define CMN_THUMB2 221
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typedef struct {
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CHAR8 *Start;
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@ -127,9 +131,9 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
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{ "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },
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{ "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },
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{ "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },
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{ "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },
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{ "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },
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{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
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@ -164,9 +168,9 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },
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{ "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },
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{ "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },
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{ "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B },
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{ "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },
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{ "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H },
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{ "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
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@ -185,6 +189,32 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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THUMB_INSTRUCTIONS gOpThumb2[] = {
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//Instruct OpCode OpCode Mask Addressig Mode
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{ "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
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{ "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, <Rm>, {,<shift> #<const>} ;Needs to go before ADD
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{ "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
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{ "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
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{ "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>
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{ "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>
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{ "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>
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{ "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>
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{ "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>
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{ "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>
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{ "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>
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{ "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>
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{ "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>
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{ "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>
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{ "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>
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{ "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>
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@ -263,6 +293,13 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "RFE" , 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}
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};
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CHAR8 *gShiftType[] = {
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"LSL",
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"LSR",
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"ASR",
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"ROR"
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};
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CHAR8 mThumbMregListStr[4*15 + 1];
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CHAR8 *
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@ -277,7 +314,7 @@ ThumbMRegList (
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Str = mThumbMregListStr;
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*Str = '\0';
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AsciiStrCat (Str, "{");
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// R0 - R7, PC
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for (Index = 0, First = TRUE; Index <= 15; Index++) {
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if ((RegBitMask & (1 << Index)) != 0) {
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Start = End = Index;
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@ -327,6 +364,18 @@ SignExtend32 (
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return Data;
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}
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//
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// Some instructions specify the PC is always considered aligned
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// The PC is after the instruction that is excuting. So you pass
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// in the instruction address and you get back the aligned answer
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//
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PCAlign4 (
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IN UINT32 Data
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)
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{
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return (Data + 4) & 0xfffffffc;
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}
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/**
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Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
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point to next instructin.
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@ -389,6 +438,15 @@ DisassembleThumbInstruction (
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// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
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return;
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case LOAD_STORE_FORMAT1_H:
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// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3f);
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return;
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case LOAD_STORE_FORMAT1_B:
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// A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
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return;
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case LOAD_STORE_FORMAT2:
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// A6.5.1 <Rd>, [<Rn>, <Rm>]
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
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@ -396,12 +454,12 @@ DisassembleThumbInstruction (
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case LOAD_STORE_FORMAT3:
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// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PC + 2 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
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return;
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case LOAD_STORE_FORMAT4:
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// Rt, [SP, #imm8]
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target, PC + 2 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
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return;
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case LOAD_STORE_MULTIPLE_FORMAT1:
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@ -499,7 +557,7 @@ DisassembleThumbInstruction (
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case ADR_FORMAT:
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// ADR <Rd>, <Label>
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PC + 4 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
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return;
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}
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}
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@ -510,6 +568,7 @@ DisassembleThumbInstruction (
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*OpCodePtrPtr += 1;
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Rt = (OpCode32 >> 12) & 0xf;
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Rt2 = (OpCode32 >> 8) & 0xf;
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Rd = (OpCode32 >> 8) & 0xf;
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Rm = (OpCode32 & 0xf);
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Rn = (OpCode32 >> 16) & 0xf;
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for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
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@ -546,8 +605,8 @@ DisassembleThumbInstruction (
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return;
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case BL_T2:
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// S:I1:I2:imm10:imm11:00
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Target = ((OpCode32 << 2) & 0x1ffc) + ((OpCode32 >> 3) & 0x7fe000);
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// BLX S:I1:I2:imm10:imm11:0
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Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
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S = (OpCode32 & BIT26) == BIT26;
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J1 = (OpCode32 & BIT13) == BIT13;
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J2 = (OpCode32 & BIT11) == BIT11;
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@ -555,7 +614,7 @@ DisassembleThumbInstruction (
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Target |= (!(J1 ^ S) ? BIT24 : 0); // I1
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Target |= (S ? BIT25 : 0); // S
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Target = SignExtend32 (Target, BIT25);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
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return;
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case POP_T2:
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@ -571,7 +630,7 @@ DisassembleThumbInstruction (
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case STM_FORMAT:
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// <Rn>{!}, <registers>
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W = (OpCode32 & BIT21) == BIT21;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
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return;
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case LDM_REG_IMM12_SIGNED:
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@ -581,7 +640,7 @@ DisassembleThumbInstruction (
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// U == 0 means subtrack, U == 1 means add
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Target = -Target;
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}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PC + 4 + Target);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);
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return;
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case LDM_REG_INDIRECT_LSL:
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@ -605,6 +664,7 @@ DisassembleThumbInstruction (
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return;
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case LDM_REG_IMM8:
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ASSERT (FALSE);
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// <rt>, [<rn>, {, #<imm8>}]{!}
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W = (OpCode32 & BIT8) == BIT8;
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U = (OpCode32 & BIT9) == BIT9;
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@ -614,10 +674,10 @@ DisassembleThumbInstruction (
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if ((OpCode32 && 0xff) == 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");
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} else {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", OpCode32 & 0xff, U?"":"-" ,W?"!":"");
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AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", OpCode32 & 0xff, U?"":"-" , W?"!":"");
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}
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} else {
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AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x]%a", OpCode32 & 0xff, U?"":"-");
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AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x]", OpCode32 & 0xff, U?"":"-");
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}
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return;
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@ -671,6 +731,49 @@ DisassembleThumbInstruction (
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
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return;
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case ADD_IMM12:
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// ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, #0x%x", gReg[Rd], gReg[Rn], Target);
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return;
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case ADD_IMM5:
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// ADC <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
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if (Target != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
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}
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return;
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case ADR_THUMB2:
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// ADDR <Rd>, <label>
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Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
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Target = PCAlign4 (PC) - Target;
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} else {
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Target = PCAlign4 (PC) + Target;
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}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
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return;
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case CMN_THUMB2:
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// CMN <Rn>, <Rm>, {,<shift> #<const>}
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a", gReg[Rn], gReg[Rm]);
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if (Target != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
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}
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return;
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}
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}
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}
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@ -38,6 +38,7 @@
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PcdLib
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PrintLib
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SemihostLib
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DebugLib
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[Pcd.common]
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gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel
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