mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg VTF0 X64: Build page tables in NASM code
Previously, we would build the page tables in Tools/FixupForRawSection.py. In order to let NASM build VTF0 from source during the EDK II build process, we need to move this into the VTF0 NASM code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15822 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jordan Justen
jljusten
parent
5a1f324d94
commit
eee1d2ca90
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@ -2,7 +2,7 @@
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; @file
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; First code executed by processor after resetting.
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;
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; Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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@ -17,6 +17,19 @@ BITS 16
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ALIGN 16
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;
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; Pad the image size to 4k when page tables are in VTF0
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;
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; If the VTF0 image has page tables built in, then we need to make
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; sure the end of VTF0 is 4k above where the page tables end.
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;
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; This is required so the page tables will be 4k aligned when VTF0 is
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; located just below 0x100000000 (4GB) in the firmware device.
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;
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%ifdef ALIGN_TOP_TO_4K_FOR_PAGING
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TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0
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%endif
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applicationProcessorEntryPoint:
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;
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; Application Processors entry point
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@ -25,7 +38,7 @@ applicationProcessorEntryPoint:
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; location. (0xffffffe0) This allows the Local APIC Startup IPI to be
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; used to wake up the application processors.
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;
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jmp short EarlyApInitReal16
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jmp EarlyApInitReal16
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ALIGN 8
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@ -50,7 +63,7 @@ resetVector:
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;
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nop
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nop
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jmp short EarlyBspInitReal16
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jmp EarlyBspInitReal16
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ALIGN 16
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@ -21,9 +21,9 @@ BITS 32
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SetCr3ForPageTables64:
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;
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; These pages are built into the ROM image by Tools/FixupForRawSection.py
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; These pages are built into the ROM image in X64/PageTables.asm
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;
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mov eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000)
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mov eax, ADDR_OF(TopLevelPageDirectory)
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mov cr3, eax
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OneTimeCallRet SetCr3ForPageTables64
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@ -16,95 +16,11 @@ import sys
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filename = sys.argv[1]
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if filename.lower().find('ia32') >= 0:
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d = open(sys.argv[1], 'rb').read()
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c = ((len(d) + 4 + 7) & ~7) - 4
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if c > len(d):
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c -= len(d)
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f = open(sys.argv[1], 'wb')
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f.write('\x90' * c)
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f.write(d)
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f.close()
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else:
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from struct import pack
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PAGE_PRESENT = 0x01
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PAGE_READ_WRITE = 0x02
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PAGE_USER_SUPERVISOR = 0x04
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PAGE_WRITE_THROUGH = 0x08
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PAGE_CACHE_DISABLE = 0x010
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PAGE_ACCESSED = 0x020
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PAGE_DIRTY = 0x040
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PAGE_PAT = 0x080
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PAGE_GLOBAL = 0x0100
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PAGE_2M_MBO = 0x080
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PAGE_2M_PAT = 0x01000
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def NopAlign4k(s):
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c = ((len(s) + 0xfff) & ~0xfff) - len(s)
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return ('\x90' * c) + s
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def PageDirectoryEntries4GbOf2MbPages(baseAddress):
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s = ''
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for i in range(0x800):
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i = (
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baseAddress + long(i << 21) +
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PAGE_2M_MBO +
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PAGE_CACHE_DISABLE +
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PAGE_ACCESSED +
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PAGE_DIRTY +
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PAGE_READ_WRITE +
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PAGE_PRESENT
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)
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s += pack('Q', i)
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return s
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def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
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s = ''
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for i in range(0x200):
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i = (
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pdeBase +
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(min(i, 3) << 12) +
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PAGE_CACHE_DISABLE +
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PAGE_ACCESSED +
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PAGE_READ_WRITE +
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PAGE_PRESENT
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)
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s += pack('Q', i)
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return s
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def PageMapLevel4Table4GbOf2MbPages(pdptBase):
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s = ''
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for i in range(0x200):
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i = (
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pdptBase +
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(min(i, 0) << 12) +
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PAGE_CACHE_DISABLE +
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PAGE_ACCESSED +
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PAGE_READ_WRITE +
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PAGE_PRESENT
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)
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s += pack('Q', i)
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return s
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def First4GbPageEntries(topAddress):
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PDE = PageDirectoryEntries4GbOf2MbPages(0L)
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pml4tBase = topAddress - 0x1000
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pdptBase = pml4tBase - 0x1000
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pdeBase = pdptBase - len(PDE)
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PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
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PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
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return PDE + PDPT + PML4T
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def AlignAndAddPageTables():
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d = open(sys.argv[1], 'rb').read()
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code = NopAlign4k(d)
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topAddress = 0x100000000 - len(code)
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d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
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f = open(sys.argv[1], 'wb')
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f.write(d)
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f.close()
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AlignAndAddPageTables()
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d = open(sys.argv[1], 'rb').read()
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c = ((len(d) + 4 + 7) & ~7) - 4
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if c > len(d):
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c -= len(d)
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f = open(sys.argv[1], 'wb')
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f.write('\x90' * c)
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f.write(d)
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f.close()
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@ -41,6 +41,10 @@
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%include "PostCodes.inc"
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%ifdef ARCH_X64
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%include "X64/PageTables.asm"
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%endif
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%ifdef DEBUG_PORT80
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%include "Port80Debug.asm"
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%elifdef DEBUG_SERIAL
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@ -0,0 +1,78 @@
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;------------------------------------------------------------------------------
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; @file
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; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
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;
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; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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BITS 64
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%define ALIGN_TOP_TO_4K_FOR_PAGING
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%define PAGE_PRESENT 0x01
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%define PAGE_READ_WRITE 0x02
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%define PAGE_USER_SUPERVISOR 0x04
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%define PAGE_WRITE_THROUGH 0x08
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%define PAGE_CACHE_DISABLE 0x010
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%define PAGE_ACCESSED 0x020
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%define PAGE_DIRTY 0x040
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%define PAGE_PAT 0x080
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%define PAGE_GLOBAL 0x0100
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%define PAGE_2M_MBO 0x080
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%define PAGE_2M_PAT 0x01000
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%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
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%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
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%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
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PAGE_PDP_ATTR)
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%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
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TopLevelPageDirectory:
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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DQ PDP(0x1000)
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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TIMES 0x1000-PGTBLS_OFFSET($) DB 0
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DQ PDP(0x2000)
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DQ PDP(0x3000)
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DQ PDP(0x4000)
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DQ PDP(0x5000)
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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TIMES 0x2000-PGTBLS_OFFSET($) DB 0
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%assign i 0
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%rep 0x800
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DQ PTE_2MB(i)
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%assign i i+1
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%endrep
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EndOfPageTables:
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