UefiCpuPkg VTF0 X64: Build page tables in NASM code

Previously, we would build the page tables in
Tools/FixupForRawSection.py.

In order to let NASM build VTF0 from source during the EDK II build
process, we need to move this into the VTF0 NASM code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15822 6f19259b-4bc3-4df7-8a09-765794883524

UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm

@@ -2,7 +2,7 @@
 ; @file
 ; First code executed by processor after resetting.
 ;
-; Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD License
 ; which accompanies this distribution.  The full text of the license may be found at
@@ -17,6 +17,19 @@ BITS    16
 
 ALIGN   16
 
+;
+; Pad the image size to 4k when page tables are in VTF0
+;
+; If the VTF0 image has page tables built in, then we need to make
+; sure the end of VTF0 is 4k above where the page tables end.
+;
+; This is required so the page tables will be 4k aligned when VTF0 is
+; located just below 0x100000000 (4GB) in the firmware device.
+;
+%ifdef ALIGN_TOP_TO_4K_FOR_PAGING
+    TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0
+%endif
+
 applicationProcessorEntryPoint:
 ;
 ; Application Processors entry point
@@ -25,7 +38,7 @@ applicationProcessorEntryPoint:
 ; location.  (0xffffffe0)  This allows the Local APIC Startup IPI to be
 ; used to wake up the application processors.
 ;
-    jmp     short EarlyApInitReal16
+    jmp     EarlyApInitReal16
 
 ALIGN   8
 
@@ -50,7 +63,7 @@ resetVector:
 ;
     nop
     nop
-    jmp     short EarlyBspInitReal16
+    jmp     EarlyBspInitReal16
 
 ALIGN   16
 

UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm

@@ -21,9 +21,9 @@ BITS    32
 SetCr3ForPageTables64:
 
     ;
-    ; These pages are built into the ROM image by Tools/FixupForRawSection.py
+    ; These pages are built into the ROM image in X64/PageTables.asm
     ;
-    mov     eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000)
+    mov     eax, ADDR_OF(TopLevelPageDirectory)
     mov     cr3, eax
 
     OneTimeCallRet SetCr3ForPageTables64

UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py

@@ -16,95 +16,11 @@ import sys
 
 filename = sys.argv[1]
 
-if filename.lower().find('ia32') >= 0:
+d = open(sys.argv[1], 'rb').read()
-    d = open(sys.argv[1], 'rb').read()
+c = ((len(d) + 4 + 7) & ~7) - 4
-    c = ((len(d) + 4 + 7) & ~7) - 4
+if c > len(d):
-    if c > len(d):
     c -= len(d)
     f = open(sys.argv[1], 'wb')
     f.write('\x90' * c)
     f.write(d)
     f.close()
-else:
-    from struct import pack
-
-    PAGE_PRESENT             =     0x01
-    PAGE_READ_WRITE          =     0x02
-    PAGE_USER_SUPERVISOR     =     0x04
-    PAGE_WRITE_THROUGH       =     0x08
-    PAGE_CACHE_DISABLE       =    0x010
-    PAGE_ACCESSED            =    0x020
-    PAGE_DIRTY               =    0x040
-    PAGE_PAT                 =    0x080
-    PAGE_GLOBAL              =   0x0100
-    PAGE_2M_MBO              =    0x080
-    PAGE_2M_PAT              =  0x01000
-
-    def NopAlign4k(s):
-        c = ((len(s) + 0xfff) & ~0xfff) - len(s)
-        return ('\x90' * c) + s
-
-    def PageDirectoryEntries4GbOf2MbPages(baseAddress):
-
-        s = ''
-        for i in range(0x800):
-            i = (
-                    baseAddress + long(i << 21) +
-                    PAGE_2M_MBO +
-                    PAGE_CACHE_DISABLE +
-                    PAGE_ACCESSED +
-                    PAGE_DIRTY +
-                    PAGE_READ_WRITE +
-                    PAGE_PRESENT
-                )
-            s += pack('Q', i)
-        return s
-
-    def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
-        s = ''
-        for i in range(0x200):
-            i = (
-                    pdeBase +
-                    (min(i, 3) << 12) +
-                    PAGE_CACHE_DISABLE +
-                    PAGE_ACCESSED +
-                    PAGE_READ_WRITE +
-                    PAGE_PRESENT
-                )
-            s += pack('Q', i)
-        return s
-
-    def PageMapLevel4Table4GbOf2MbPages(pdptBase):
-        s = ''
-        for i in range(0x200):
-            i = (
-                    pdptBase +
-                    (min(i, 0) << 12) +
-                    PAGE_CACHE_DISABLE +
-                    PAGE_ACCESSED +
-                    PAGE_READ_WRITE +
-                    PAGE_PRESENT
-                )
-            s += pack('Q', i)
-        return s
-
-    def First4GbPageEntries(topAddress):
-        PDE = PageDirectoryEntries4GbOf2MbPages(0L)
-        pml4tBase = topAddress - 0x1000
-        pdptBase = pml4tBase - 0x1000
-        pdeBase = pdptBase - len(PDE)
-        PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
-        PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
-        return PDE + PDPT + PML4T
-
-    def AlignAndAddPageTables():
-        d = open(sys.argv[1], 'rb').read()
-        code = NopAlign4k(d)
-        topAddress = 0x100000000 - len(code)
-        d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
-        f = open(sys.argv[1], 'wb')
-        f.write(d)
-        f.close()
-
-    AlignAndAddPageTables()
-

UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb

@@ -41,6 +41,10 @@
 
 %include "PostCodes.inc"
 
+%ifdef ARCH_X64
+%include "X64/PageTables.asm"
+%endif
+
 %ifdef DEBUG_PORT80
   %include "Port80Debug.asm"
 %elifdef DEBUG_SERIAL

UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm

@@ -0,0 +1,78 @@
+;------------------------------------------------------------------------------
+; @file
+; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
+;
+; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+BITS    64
+
+%define ALIGN_TOP_TO_4K_FOR_PAGING
+
+%define PAGE_PRESENT            0x01
+%define PAGE_READ_WRITE         0x02
+%define PAGE_USER_SUPERVISOR    0x04
+%define PAGE_WRITE_THROUGH      0x08
+%define PAGE_CACHE_DISABLE     0x010
+%define PAGE_ACCESSED          0x020
+%define PAGE_DIRTY             0x040
+%define PAGE_PAT               0x080
+%define PAGE_GLOBAL           0x0100
+%define PAGE_2M_MBO            0x080
+%define PAGE_2M_PAT          0x01000
+
+%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
+                          PAGE_ACCESSED + \
+                          PAGE_DIRTY + \
+                          PAGE_READ_WRITE + \
+                          PAGE_PRESENT)
+
+%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
+                       PAGE_READ_WRITE + \
+                       PAGE_PRESENT)
+
+%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
+%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
+
+%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+                     PAGE_PDP_ATTR)
+%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
+
+TopLevelPageDirectory:
+
+    ;
+    ; Top level Page Directory Pointers (1 * 512GB entry)
+    ;
+    DQ      PDP(0x1000)
+
+
+    ;
+    ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
+    ;
+    TIMES 0x1000-PGTBLS_OFFSET($) DB 0
+
+    DQ      PDP(0x2000)
+    DQ      PDP(0x3000)
+    DQ      PDP(0x4000)
+    DQ      PDP(0x5000)
+
+    ;
+    ; Page Table Entries (2048 * 2MB entries => 4GB)
+    ;
+    TIMES 0x2000-PGTBLS_OFFSET($) DB 0
+
+%assign i 0
+%rep    0x800
+    DQ      PTE_2MB(i)
+    %assign i i+1
+%endrep
+
+EndOfPageTables: