mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR0.WP before modify page table
Clear CR0.WP before modify smm page table. Currently, there is an assumption that smm pagetable is always RW before ReadyToLock. However, when AMD SEV is enabled, FvbServicesSmm driver calls MemEncryptSevClearMmioPageEncMask to clear AddressEncMask bit in smm page table for this range: [PcdOvmfFdBaseAddress,PcdOvmfFdBaseAddress+PcdOvmfFirmwareFdSize] If page slpit happens in this process, new memory for smm page table is allocated. Then the newly allocated page table memory is marked as RO in smm page table in this FvbServicesSmm driver, which may lead to PF if smm code doesn't clear CR0.WP before modify smm page table when ReadyToLock. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
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@ -1033,6 +1033,8 @@ SetMemMapAttributes (
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IA32_MAP_ENTRY *Map;
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UINTN Count;
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UINT64 MemoryAttribute;
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BOOLEAN WpEnabled;
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BOOLEAN CetEnabled;
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SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);
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if (MemoryAttributesTable == NULL) {
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@ -1077,6 +1079,8 @@ SetMemMapAttributes (
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ASSERT_RETURN_ERROR (Status);
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DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled);
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MemoryMap = MemoryMapStart;
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for (Index = 0; Index < MemoryMapEntryCount; Index++) {
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DEBUG ((DEBUG_VERBOSE, "SetAttribute: Memory Entry - 0x%lx, 0x%x\n", MemoryMap->PhysicalStart, MemoryMap->NumberOfPages));
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@ -1105,6 +1109,7 @@ SetMemMapAttributes (
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MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);
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}
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EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled);
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FreePool (Map);
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PatchSmmSaveStateMap ();
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@ -1411,11 +1416,15 @@ SetUefiMemMapAttributes (
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UINTN MemoryMapEntryCount;
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UINTN Index;
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EFI_MEMORY_DESCRIPTOR *Entry;
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BOOLEAN WpEnabled;
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BOOLEAN CetEnabled;
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PERF_FUNCTION_BEGIN ();
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DEBUG ((DEBUG_INFO, "SetUefiMemMapAttributes\n"));
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DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled);
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if (mUefiMemoryMap != NULL) {
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MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize;
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MemoryMap = mUefiMemoryMap;
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@ -1494,6 +1503,8 @@ SetUefiMemMapAttributes (
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}
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}
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EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled);
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//
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// Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress().
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//
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@ -574,6 +574,8 @@ InitPaging (
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BOOLEAN Nx;
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IA32_CR4 Cr4;
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BOOLEAN Enable5LevelPaging;
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BOOLEAN WpEnabled;
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BOOLEAN CetEnabled;
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PERF_FUNCTION_BEGIN ();
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@ -622,6 +624,7 @@ InitPaging (
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NumberOfPdptEntries = 4;
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}
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DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled);
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//
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// Go through page table and change 2MB-page into 4KB-page.
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//
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@ -802,6 +805,8 @@ InitPaging (
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} // end for PML4
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} // end for PML5
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EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled);
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//
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// Flush TLB
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//
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