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ArmPlatformPkg: Juno - add correct SPI interrupt numbers for MSI 

The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware
that has some memory mapped locations that can trigger traditional SPI
interrupts. This allows some basic PCIe MSI capabilities.

Setup the SPI range that is mapped by the MSI window. This range is
described in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is
described as "GICv2m PCI Express MSI". In the future when these tables
are generated programmatically the information may be found in the
MSI_TYPER register as well.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18723 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeremy Linton 2015-11-03 11:11:22 +00:00 committed by leiflindholm
parent fad21b7c57
commit efcc052bdf
2 changed files with 7 additions and 1 deletions
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3
ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc
View File

@ -119,7 +119,8 @@
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
}, },
EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0), EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),
EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, 0, 0) // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)
EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)
}; };
#endif #endif

5
ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h
View File

@ -40,9 +40,14 @@
#define ARM_JUNO_PERIPHERALS_BASE 0x20000000 #define ARM_JUNO_PERIPHERALS_BASE 0x20000000
#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000 #define ARM_JUNO_PERIPHERALS_SZ 0x0E000000
// PCIe MSI address window
#define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000 #define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000
#define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB #define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB
// PCIe MSI to SPI mapping range
#define ARM_JUNO_GIV2M_MSI_SPI_BASE 224
#define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is 351, 351-224=127
// On-Chip non-secure SRAM // On-Chip non-secure SRAM
#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000 #define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000
#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB #define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB