ArmPkg/ArmLib: ArmReadVBar implementation missing in AArch64

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15274 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-03-01 10:58:46 +00:00 committed by oliviermartin
parent eaa84fd553
commit f0247796cb
1 changed files with 11 additions and 0 deletions

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@ -45,6 +45,7 @@ GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT (ArmWriteVBar) GCC_ASM_EXPORT (ArmWriteVBar)
GCC_ASM_EXPORT (ArmReadVBar)
GCC_ASM_EXPORT (ArmVFPImplemented) GCC_ASM_EXPORT (ArmVFPImplemented)
GCC_ASM_EXPORT (ArmEnableVFP) GCC_ASM_EXPORT (ArmEnableVFP)
GCC_ASM_EXPORT (ArmCallWFI) GCC_ASM_EXPORT (ArmCallWFI)
@ -411,6 +412,16 @@ ASM_PFX(ArmWriteVBar):
4: isb 4: isb
ret ret
ASM_PFX(ArmReadVBar):
EL1_OR_EL2_OR_EL3(x1)
1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register
ret
2: mrs x0, vbar_el2 // Set the Address of the EL2 Vector Table in the VBAR register
ret
3: mrs x0, vbar_el3 // Set the Address of the EL3 Vector Table in the VBAR register
ret
ASM_PFX(ArmEnableVFP): ASM_PFX(ArmEnableVFP):
// Check whether floating-point is implemented in the processor. // Check whether floating-point is implemented in the processor.
mov x1, x30 // Save LR mov x1, x30 // Save LR