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ArmPkg/CompilerIntrinsincsLib: Add div and mullu functions to ARMGCC
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11742 6f19259b-4bc3-4df7-8a09-765794883524
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ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.S
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156
ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.S
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2011, ARM. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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GCC_ASM_EXPORT(__aeabi_uidiv)
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GCC_ASM_EXPORT(__aeabi_uidivmod)
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GCC_ASM_EXPORT(__aeabi_idiv)
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GCC_ASM_EXPORT(__aeabi_idivmod)
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# AREA Math, CODE, READONLY
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#
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#UINT32
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#EFIAPI
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#__aeabi_uidivmode (
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# IN UINT32 Dividen
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# IN UINT32 Divisor
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# );
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#
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ASM_PFX(__aeabi_uidiv):
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ASM_PFX(__aeabi_uidivmod):
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RSBS r12, r1, r0, LSR #4
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MOV r2, #0
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BCC ASM_PFX(__arm_div4)
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RSBS r12, r1, r0, LSR #8
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BCC ASM_PFX(__arm_div8)
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MOV r3, #0
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B ASM_PFX(__arm_div_large)
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#
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#INT32
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#EFIAPI
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#__aeabi_idivmode (
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# IN INT32 Dividen
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# IN INT32 Divisor
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# );
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#
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ASM_PFX(__aeabi_idiv):
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ASM_PFX(__aeabi_idivmod):
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ORRS r12, r0, r1
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BMI ASM_PFX(__arm_div_negative)
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RSBS r12, r1, r0, LSR #1
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MOV r2, #0
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BCC ASM_PFX(__arm_div1)
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RSBS r12, r1, r0, LSR #4
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BCC ASM_PFX(__arm_div4)
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RSBS r12, r1, r0, LSR #8
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BCC ASM_PFX(__arm_div8)
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MOV r3, #0
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B ASM_PFX(__arm_div_large)
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ASM_PFX(__arm_div8):
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RSBS r12, r1, r0, LSR #7
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SUBCS r0, r0, r1, LSL #7
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ADC r2, r2, r2
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RSBS r12, r1, r0,LSR #6
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SUBCS r0, r0, r1, LSL #6
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #5
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SUBCS r0, r0, r1, LSL #5
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #4
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SUBCS r0, r0, r1, LSL #4
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ADC r2, r2, r2
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ASM_PFX(__arm_div4):
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RSBS r12, r1, r0, LSR #3
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SUBCS r0, r0, r1, LSL #3
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #2
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SUBCS r0, r0, r1, LSL #2
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ADCS r2, r2, r2
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RSBS r12, r1, r0, LSR #1
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SUBCS r0, r0, r1, LSL #1
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ADC r2, r2, r2
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ASM_PFX(__arm_div1):
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SUBS r1, r0, r1
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MOVCC r1, r0
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ADC r0, r2, r2
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BX r14
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ASM_PFX(__arm_div_negative):
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ANDS r2, r1, #0x80000000
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RSBMI r1, r1, #0
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EORS r3, r2, r0, ASR #32
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RSBCS r0, r0, #0
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RSBS r12, r1, r0, LSR #4
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BCC label1
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RSBS r12, r1, r0, LSR #8
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BCC label2
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ASM_PFX(__arm_div_large):
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LSL r1, r1, #6
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RSBS r12, r1, r0, LSR #8
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ORR r2, r2, #0xfc000000
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BCC label2
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LSL r1, r1, #6
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RSBS r12, r1, r0, LSR #8
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ORR r2, r2, #0x3f00000
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BCC label2
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LSL r1, r1, #6
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RSBS r12, r1, r0, LSR #8
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ORR r2, r2, #0xfc000
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ORRCS r2, r2, #0x3f00
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LSLCS r1, r1, #6
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RSBS r12, r1, #0
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BCS ASM_PFX(__aeabi_idiv0)
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label3:
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LSRCS r1, r1, #6
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label2:
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RSBS r12, r1, r0, LSR #7
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SUBCS r0, r0, r1, LSL #7
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #6
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SUBCS r0, r0, r1, LSL #6
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #5
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SUBCS r0, r0, r1, LSL #5
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #4
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SUBCS r0, r0, r1, LSL #4
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ADC r2, r2, r2
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label1:
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RSBS r12, r1, r0, LSR #3
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SUBCS r0, r0, r1, LSL #3
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ADC r2, r2, r2
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RSBS r12, r1, r0, LSR #2
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SUBCS r0, r0, r1, LSL #2
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ADCS r2, r2, r2
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BCS label3
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RSBS r12, r1, r0, LSR #1
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SUBCS r0, r0, r1, LSL #1
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ADC r2, r2, r2
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SUBS r1, r0, r1
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MOVCC r1, r0
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ADC r0, r2, r2
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ASRS r3, r3, #31
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RSBMI r0, r0, #0
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RSBCS r1, r1, #0
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BX r14
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@ What to do about division by zero? For now, just return.
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ASM_PFX(__aeabi_idiv0):
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BX r14
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.end
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46
ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.S
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46
ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.S
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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GCC_ASM_EXPORT(__ARM_ll_mullu)
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GCC_ASM_EXPORT(__aeabi_lmul)
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#
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#INT64
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#EFIAPI
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#__aeabi_lmul (
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# IN INT64 Multiplicand
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# IN INT32 Multiplier
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# );
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#
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ASM_PFX(__ARM_ll_mullu):
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mov r3, #0
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# Make upper part of INT64 Multiplier 0 and use __aeabi_lmul
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#
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#INT64
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#EFIAPI
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#__aeabi_lmul (
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# IN INT64 Multiplicand
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# IN INT64 Multiplier
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# );
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#
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ASM_PFX(__aeabi_lmul):
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stmdb sp!, {lr}
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mov lr, r0
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umull r0, ip, r2, lr
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mla r1, r2, r1, ip
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mla r1, r3, lr, r1
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ldmia sp!, {pc}
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.end
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@ -51,6 +51,7 @@
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# Arm/lshrdi3.c | GCC
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Arm/ashrdi3.S | GCC
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Arm/ashldi3.S | GCC
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Arm/div.S | GCC
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Arm/divdi3.S | GCC
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Arm/divsi3.S | GCC
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Arm/lshrdi3.S | GCC
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@ -63,7 +64,8 @@
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# Arm/muldi3.c | GCC
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Arm/modsi3.S | GCC
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Arm/moddi3.S | GCC
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Arm/muldi3.S | GCC
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Arm/muldi3.S | GCC
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Arm/mullu.S | GCC
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# Arm/udivsi3.c | GCC
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# Arm/umodsi3.c | GCC
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