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MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1537

Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register
accesses from being split up into 8-bit accesses.

The SDHCI specification states that the registers shall be accessible in
byte, word, and double word accesses. (SD Host Controller Simplified
Specification 4.20 Section 1.2)

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Edgar Handal 2019-02-20 01:06:56 +08:00 committed by Hao Wu
parent 195f673f62
commit f168816c49
1 changed files with 21 additions and 4 deletions
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23
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
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@ -154,19 +154,36 @@ SdMmcHcRwMmio (
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL_WIDTH Width;
if ((PciIo == NULL) || (Data == NULL)) { if ((PciIo == NULL) || (Data == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) { switch (Count) {
case 1:
Width = EfiPciIoWidthUint8;
break;
case 2:
Width = EfiPciIoWidthUint16;
Count = 1;
break;
case 4:
Width = EfiPciIoWidthUint32;
Count = 1;
break;
case 8:
Width = EfiPciIoWidthUint32;
Count = 2;
break;
default:
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (Read) { if (Read) {
Status = PciIo->Mem.Read ( Status = PciIo->Mem.Read (
PciIo, PciIo,
EfiPciIoWidthUint8, Width,
BarIndex, BarIndex,
(UINT64) Offset, (UINT64) Offset,
Count, Count,
@ -175,7 +192,7 @@ SdMmcHcRwMmio (
} else { } else {
Status = PciIo->Mem.Write ( Status = PciIo->Mem.Write (
PciIo, PciIo,
EfiPciIoWidthUint8, Width,
BarIndex, BarIndex,
(UINT64) Offset, (UINT64) Offset,
Count, Count,