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MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1537 Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register accesses from being split up into 8-bit accesses. The SDHCI specification states that the registers shall be accessible in byte, word, and double word accesses. (SD Host Controller Simplified Specification 4.20 Section 1.2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
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@ -154,19 +154,36 @@ SdMmcHcRwMmio (
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)
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)
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{
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{
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EFI_STATUS Status;
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL_WIDTH Width;
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if ((PciIo == NULL) || (Data == NULL)) {
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if ((PciIo == NULL) || (Data == NULL)) {
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return EFI_INVALID_PARAMETER;
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return EFI_INVALID_PARAMETER;
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}
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}
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if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
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switch (Count) {
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case 1:
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Width = EfiPciIoWidthUint8;
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break;
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case 2:
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Width = EfiPciIoWidthUint16;
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Count = 1;
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break;
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case 4:
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Width = EfiPciIoWidthUint32;
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Count = 1;
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break;
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case 8:
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Width = EfiPciIoWidthUint32;
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Count = 2;
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break;
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default:
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return EFI_INVALID_PARAMETER;
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return EFI_INVALID_PARAMETER;
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}
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}
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if (Read) {
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if (Read) {
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Status = PciIo->Mem.Read (
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Status = PciIo->Mem.Read (
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PciIo,
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PciIo,
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EfiPciIoWidthUint8,
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Width,
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BarIndex,
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BarIndex,
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(UINT64) Offset,
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(UINT64) Offset,
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Count,
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Count,
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@ -175,7 +192,7 @@ SdMmcHcRwMmio (
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} else {
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} else {
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Status = PciIo->Mem.Write (
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Status = PciIo->Mem.Write (
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PciIo,
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PciIo,
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EfiPciIoWidthUint8,
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Width,
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BarIndex,
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BarIndex,
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(UINT64) Offset,
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(UINT64) Offset,
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Count,
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Count,
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