mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/CpuDxe: Refactor to use CPUID definitions
The patch does not change any code behavior but only refactors by: * replaces the hardcode 0x80000000 with CPUID_EXTENDED_FUNCTION * replaces the hardcode 0x80000008 with CPUID_VIR_PHY_ADDRESS_SIZE * replace "UINT32 Eax" with "CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize" Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
This commit is contained in:
parent
263782f667
commit
f2f526e074
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
CPU DXE Module to produce CPU ARCH Protocol.
|
||||
|
||||
Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
@ -505,20 +505,18 @@ InitializeMtrrMask (
|
|||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 RegEax;
|
||||
UINT8 PhysicalAddressBits;
|
||||
UINT32 MaxExtendedFunction;
|
||||
CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
|
||||
|
||||
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
|
||||
AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
|
||||
|
||||
if (RegEax >= 0x80000008) {
|
||||
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
|
||||
|
||||
PhysicalAddressBits = (UINT8)RegEax;
|
||||
if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
|
||||
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
|
||||
} else {
|
||||
PhysicalAddressBits = 36;
|
||||
VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
|
||||
}
|
||||
|
||||
mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
|
||||
mValidMtrrBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
|
||||
mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
|
||||
}
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.
|
||||
|
||||
Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
|
||||
**/
|
||||
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <Protocol/Cpu.h>
|
||||
#include <Protocol/MpService.h>
|
||||
#include <Register/Intel/Cpuid.h>
|
||||
#include <Register/Intel/Msr.h>
|
||||
|
||||
#include <Ppi/SecPlatformInformation.h>
|
||||
|
|
Loading…
Reference in New Issue