UefiCpuPkg/CpuDxe: Refactor to use CPUID definitions

The patch does not change any code behavior but only refactors by:
* replaces the hardcode 0x80000000 with CPUID_EXTENDED_FUNCTION
* replaces the hardcode 0x80000008 with CPUID_VIR_PHY_ADDRESS_SIZE
* replace "UINT32 Eax" with
   "CPUID_VIR_PHY_ADDRESS_SIZE_EAX  VirPhyAddressSize"

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ahmad Anadani <ahmad.anadani@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
This commit is contained in:
Ray Ni 2023-02-27 13:43:19 +08:00 committed by mergify[bot]
parent 263782f667
commit f2f526e074
2 changed files with 10 additions and 11 deletions

View File

@ -1,7 +1,7 @@
/** @file /** @file
CPU DXE Module to produce CPU ARCH Protocol. CPU DXE Module to produce CPU ARCH Protocol.
Copyright (c) 2008 - 2022, Intel Corporation. All rights reserved.<BR> Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -505,20 +505,18 @@ InitializeMtrrMask (
VOID VOID
) )
{ {
UINT32 RegEax; UINT32 MaxExtendedFunction;
UINT8 PhysicalAddressBits; CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
if (RegEax >= 0x80000008) { if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8)RegEax;
} else { } else {
PhysicalAddressBits = 36; VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
} }
mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1; mValidMtrrBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL; mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
} }

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@ -1,7 +1,7 @@
/** @file /** @file
CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol. CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.
Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.<BR> Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -13,6 +13,7 @@
#include <Protocol/Cpu.h> #include <Protocol/Cpu.h>
#include <Protocol/MpService.h> #include <Protocol/MpService.h>
#include <Register/Intel/Cpuid.h>
#include <Register/Intel/Msr.h> #include <Register/Intel/Msr.h>
#include <Ppi/SecPlatformInformation.h> #include <Ppi/SecPlatformInformation.h>