mirror of https://github.com/acidanthera/audk.git
Create X64 mode page tables in memory even when PEI is already X64
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6550 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
mdkinney
parent
d0a0826133
commit
f3b33289f0
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@ -46,6 +46,8 @@
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Ia32/IdtVectorAsm.S | GCC
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[Sources.X64, Sources.EBC]
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X64/VirtualMemory.h
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X64/VirtualMemory.c
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X64/DxeLoadFunc.c
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Ia32/ImageRead.c
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@ -13,6 +13,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DxeIpl.h"
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#include "X64/VirtualMemory.h"
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@ -36,6 +37,7 @@ HandOffToDxeCore (
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VOID *BaseOfStack;
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VOID *TopOfStack;
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EFI_STATUS Status;
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UINTN PageTables;
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//
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// Allocate 128KB for the Stack
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@ -50,12 +52,19 @@ HandOffToDxeCore (
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TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
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TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
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//
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// Create page table and save PageMapLevel4 to CR3
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//
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PageTables = CreateIdentityMappingPageTables ();
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//
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// End of PEI phase singal
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//
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Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
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ASSERT_EFI_ERROR (Status);
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AsmWriteCr3 (PageTables);
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//
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// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
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//
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@ -0,0 +1,162 @@
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/** @file
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x64 Virtual Memory Management Services in the form of an IA-32 driver.
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Used to establish a 1:1 Virtual to Physical Mapping that is required to
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enter Long Mode (x64 64-bit mode).
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While we make a 1:1 mapping (identity mapping) for all physical pages
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we still need to use the MTRR's to ensure that the cachability attirbutes
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for all memory regions is correct.
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The basic idea is to use 2MB page table entries where ever possible. If
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more granularity of cachability is required then 4K page tables are used.
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References:
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1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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Copyright (c) 2006 - 2008, Intel Corporation. <BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "DxeIpl.h"
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#include "VirtualMemory.h"
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping.
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@param NumberOfProcessorPhysicalAddressBits Number of processor address bits
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to use. Limits the number of page
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table entries to the physical
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address space.
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@return EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created
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**/
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UINTN
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CreateIdentityMappingPageTables (
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VOID
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)
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{
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UINT8 PhysicalAddressBits;
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EFI_PHYSICAL_ADDRESS PageAddress;
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UINTN IndexOfPml4Entries;
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UINTN IndexOfPdpEntries;
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UINTN IndexOfPageDirectoryEntries;
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UINTN NumberOfPml4EntriesNeeded;
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UINTN NumberOfPdpEntriesNeeded;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
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PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
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PAGE_TABLE_ENTRY *PageDirectoryEntry;
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UINTN TotalPagesNum;
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UINTN BigPageAddress;
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VOID *Hob;
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//
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// Get physical address bits supported from CPU HOB.
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//
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PhysicalAddressBits = 36;
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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}
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//
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// Calculate the table entries needed.
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//
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if (PhysicalAddressBits <= 39 ) {
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NumberOfPml4EntriesNeeded = 1;
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NumberOfPdpEntriesNeeded = LShiftU64 (1, (PhysicalAddressBits - 30));
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} else {
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NumberOfPml4EntriesNeeded = LShiftU64 (1, (PhysicalAddressBits - 39));
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NumberOfPdpEntriesNeeded = 512;
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}
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//
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// Pre-allocate big pages to avoid later allocations.
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//
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TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;
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BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);
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ASSERT (BigPageAddress != 0);
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//
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// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
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//
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PageMap = (VOID *) BigPageAddress;
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BigPageAddress += EFI_PAGE_SIZE;
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PageMapLevel4Entry = PageMap;
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PageAddress = 0;
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for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {
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//
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// Each PML4 entry points to a page of Page Directory Pointer entires.
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// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
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//
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PageDirectoryPointerEntry = (VOID *) BigPageAddress;
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BigPageAddress += EFI_PAGE_SIZE;
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//
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// Make a PML4 Entry
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//
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PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;
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PageMapLevel4Entry->Bits.ReadWrite = 1;
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PageMapLevel4Entry->Bits.Present = 1;
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for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
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//
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// Each Directory Pointer entries points to a page of Page Directory entires.
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// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
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//
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PageDirectoryEntry = (VOID *) BigPageAddress;
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BigPageAddress += EFI_PAGE_SIZE;
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//
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// Fill in a Page Directory Pointer Entries
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//
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PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;
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PageDirectoryPointerEntry->Bits.ReadWrite = 1;
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PageDirectoryPointerEntry->Bits.Present = 1;
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for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {
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//
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// Fill in the Page Directory entries
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//
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PageDirectoryEntry->Uint64 = (UINT64)PageAddress;
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PageDirectoryEntry->Bits.ReadWrite = 1;
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PageDirectoryEntry->Bits.Present = 1;
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PageDirectoryEntry->Bits.MustBe1 = 1;
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}
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}
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}
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//
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// For the PML4 entries we are not using fill in a null entry.
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// For now we just copy the first entry.
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//
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for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {
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CopyMem (
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PageMapLevel4Entry,
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PageMap,
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sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)
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);
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}
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return (UINTN)PageMap;
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}
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@ -0,0 +1,161 @@
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/** @file
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x64 Long Mode Virtual Memory Management Definitions
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References:
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1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel
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2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
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3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
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4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
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Copyright (c) 2006 - 2008, Intel Corporation. <BR>
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _VIRTUAL_MEMORY_H_
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#define _VIRTUAL_MEMORY_H_
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#define SYS_CODE64_SEL 0x38
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#pragma pack(1)
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typedef union {
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struct {
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UINT32 LimitLow : 16;
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UINT32 BaseLow : 16;
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UINT32 BaseMid : 8;
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UINT32 Type : 4;
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UINT32 System : 1;
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UINT32 Dpl : 2;
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UINT32 Present : 1;
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UINT32 LimitHigh : 4;
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UINT32 Software : 1;
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UINT32 Reserved : 1;
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UINT32 DefaultSize : 1;
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UINT32 Granularity : 1;
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UINT32 BaseHigh : 8;
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} Bits;
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UINT64 Uint64;
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} IA32_GDT;
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typedef struct {
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IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;
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UINT32 Offset32To63;
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UINT32 Reserved;
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} X64_IDT_GATE_DESCRIPTOR;
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//
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// Page-Map Level-4 Offset (PML4) and
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// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Reserved:1; // Reserved
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UINT64 MustBeZero:2; // Must Be Zero
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UINT64 Available:3; // Available for use by system software
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UINT64 PageTableBaseAddress:40; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // No Execute bit
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} Bits;
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UINT64 Uint64;
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} PAGE_MAP_AND_DIRECTORY_POINTER;
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//
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// Page Table Entry 2MB
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//
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typedef union {
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struct {
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UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
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UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
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UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
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UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
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UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
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UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
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UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
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UINT64 MustBe1:1; // Must be 1
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UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
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UINT64 Available:3; // Available for use by system software
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UINT64 PAT:1; //
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UINT64 MustBeZero:8; // Must be zero;
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UINT64 PageTableBaseAddress:31; // Page Table Base Address
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UINT64 AvabilableHigh:11; // Available for use by system software
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UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
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} Bits;
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UINT64 Uint64;
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} PAGE_TABLE_ENTRY;
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#pragma pack()
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping.
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@param NumberOfProcessorPhysicalAddressBits Number of processor address bits
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to use. Limits the number of page
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table entries to the physical
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address space.
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@return EFI_SUCCESS The 1:1 Virtual to Physical identity mapping was created
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**/
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UINTN
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CreateIdentityMappingPageTables (
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VOID
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);
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/**
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Fix up the vector number in the vector code.
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@param VectorBase Base address of the vector handler.
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@param VectorNum Index of vector.
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**/
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VOID
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EFIAPI
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AsmVectorFixup (
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VOID *VectorBase,
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UINT8 VectorNum
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);
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/**
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Get the information of vector template.
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@param TemplateBase Base address of the template code.
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@return Size of the Template code.
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**/
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UINTN
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EFIAPI
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AsmGetVectorTemplatInfo (
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OUT VOID **TemplateBase
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);
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#endif
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