mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: Renamed and Invoked earlier ArmPlatformNormalInitialize()
- ArmPlatformNormalInitialize() has been renamed into ArmPlatformInitialize() - Make the function be called at the early stage of the PEI phase as some platforms require their interconnects or clocks to be initialize before any access to Timers or UARTs. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13245 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -13,6 +13,7 @@
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**/
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#include <Library/IoLib.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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@ -68,11 +69,15 @@ ArmPlatformGetBootMode (
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in the PEI phase.
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**/
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VOID
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ArmPlatformNormalInitialize (
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VOID
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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)
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{
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if (!IS_PRIMARY_CORE(MpId)) {
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return RETURN_SUCCESS;
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}
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// Disable memory remapping and return to normal mapping
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MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
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@ -84,6 +89,8 @@ ArmPlatformNormalInitialize (
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
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// Configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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return RETURN_SUCCESS;
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}
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/**
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@ -1,5 +1,5 @@
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -41,3 +41,6 @@
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[FixedPcd]
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gArmTokenSpaceGuid.PcdSystemMemoryBase
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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@ -1,5 +1,5 @@
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -50,3 +50,6 @@
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmTokenSpaceGuid.PcdL2x0ControllerBase
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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@ -131,11 +131,15 @@ ArmPlatformGetBootMode (
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in the PEI phase.
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**/
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VOID
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ArmPlatformNormalInitialize (
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VOID
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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)
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{
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if (!IS_PRIMARY_CORE(MpId)) {
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return RETURN_SUCCESS;
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}
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// Configure periodic timer (TIMER0) for 1MHz operation
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
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// Configure 1MHz clock
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@ -144,6 +148,8 @@ ArmPlatformNormalInitialize (
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
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// Configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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return RETURN_SUCCESS;
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}
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/**
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@ -1,5 +1,5 @@
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -47,3 +47,6 @@
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gArmTokenSpaceGuid.PcdSystemMemoryBase
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmTokenSpaceGuid.PcdFvBaseAddress
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -92,13 +92,19 @@ ArmPlatformGetBootMode (
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in the PEI phase.
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**/
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VOID
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ArmPlatformNormalInitialize (
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VOID
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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)
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{
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if (!IS_PRIMARY_CORE(MpId)) {
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return RETURN_SUCCESS;
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}
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// Disable memory remapping and return to normal mapping
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MmioOr32 (SP810_CTRL_BASE, BIT8);
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return RETURN_SUCCESS;
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}
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/**
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@ -115,9 +115,9 @@ ArmPlatformSecExtraAction (
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in the PEI phase.
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**/
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VOID
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ArmPlatformNormalInitialize (
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VOID
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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);
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/**
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -92,12 +92,18 @@ ArmPlatformGetBootMode (
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in the PEI phase.
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**/
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VOID
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ArmPlatformNormalInitialize (
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VOID
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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)
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{
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if (!IS_PRIMARY_CORE(MpId)) {
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return RETURN_SUCCESS;
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}
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//TODO: Implement me
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return RETURN_SUCCESS;
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}
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/**
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -36,3 +36,6 @@
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[FixedPcd]
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gArmTokenSpaceGuid.PcdSystemMemoryBase
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -24,9 +24,6 @@ PlatformPeim (
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VOID
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)
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{
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// Initialize the platform specific controllers
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ArmPlatformNormalInitialize ();
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BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize));
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return EFI_SUCCESS;
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@ -1,6 +1,6 @@
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#/** @file
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -1,6 +1,6 @@
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#/** @file
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -100,6 +100,9 @@ CEntryPoint (
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InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
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SaveAndSetDebugTimerInterrupt (TRUE);
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// Initialize the platform specific controllers
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ArmPlatformInitialize (MpId);
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// Goto primary Main.
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PrimaryMain (PeiCoreEntryPoint);
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} else {
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -175,6 +175,9 @@ CEntryPoint (
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{
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UINT64 StartTimeStamp;
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// Initialize the platform specific controllers
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ArmPlatformInitialize (MpId);
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if (IS_PRIMARY_CORE(MpId) && PerformanceMeasurementEnabled ()) {
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// Initialize the Timer Library to setup the Timer HW controller
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TimerConstructor ();
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -110,9 +110,9 @@ ArmPlatformGetBootMode (
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For example, some L2x0 requires to be initialized in Secure World
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**/
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VOID
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ArmPlatformNormalInitialize (
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VOID
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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)
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{
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BEAGLEBOARD_REVISION Revision;
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// Clear IRQs
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MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
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ArmDataSyncronizationBarrier ();
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return RETURN_SUCCESS;
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}
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/**
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