ArmPlatformPkg: Renamed and Invoked earlier ArmPlatformNormalInitialize()

- ArmPlatformNormalInitialize() has been renamed into ArmPlatformInitialize()
- Make the function be called at the early stage of the PEI phase as some
  platforms require their interconnects or clocks to be initialize before any
  access to Timers or UARTs.

Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13245 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-05-02 19:49:35 +00:00
parent e9f7c58f25
commit f437141a9c
15 changed files with 75 additions and 33 deletions

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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -13,6 +13,7 @@
**/ **/
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/ArmLib.h>
#include <Library/ArmPlatformLib.h> #include <Library/ArmPlatformLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
@ -68,11 +69,15 @@ ArmPlatformGetBootMode (
in the PEI phase. in the PEI phase.
**/ **/
VOID RETURN_STATUS
ArmPlatformNormalInitialize ( ArmPlatformInitialize (
VOID IN UINTN MpId
) )
{ {
if (!IS_PRIMARY_CORE(MpId)) {
return RETURN_SUCCESS;
}
// Disable memory remapping and return to normal mapping // Disable memory remapping and return to normal mapping
MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
@ -84,6 +89,8 @@ ArmPlatformNormalInitialize (
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
// Configure SP810 to use 1MHz clock and disable // Configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
return RETURN_SUCCESS;
} }
/** /**

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@ -1,5 +1,5 @@
#/* @file #/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011-2012, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -41,3 +41,6 @@
[FixedPcd] [FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

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@ -1,5 +1,5 @@
#/* @file #/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011-2012, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -50,3 +50,6 @@
gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdL2x0ControllerBase gArmTokenSpaceGuid.PcdL2x0ControllerBase
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

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@ -131,11 +131,15 @@ ArmPlatformGetBootMode (
in the PEI phase. in the PEI phase.
**/ **/
VOID RETURN_STATUS
ArmPlatformNormalInitialize ( ArmPlatformInitialize (
VOID IN UINTN MpId
) )
{ {
if (!IS_PRIMARY_CORE(MpId)) {
return RETURN_SUCCESS;
}
// Configure periodic timer (TIMER0) for 1MHz operation // Configure periodic timer (TIMER0) for 1MHz operation
MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
// Configure 1MHz clock // Configure 1MHz clock
@ -144,6 +148,8 @@ ArmPlatformNormalInitialize (
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
// Configure SP810 to use 1MHz clock and disable // Configure SP810 to use 1MHz clock and disable
MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
return RETURN_SUCCESS;
} }
/** /**

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@ -1,5 +1,5 @@
#/* @file #/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011-2012, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -47,3 +47,6 @@
gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdFvBaseAddress gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -92,13 +92,19 @@ ArmPlatformGetBootMode (
in the PEI phase. in the PEI phase.
**/ **/
VOID RETURN_STATUS
ArmPlatformNormalInitialize ( ArmPlatformInitialize (
VOID IN UINTN MpId
) )
{ {
if (!IS_PRIMARY_CORE(MpId)) {
return RETURN_SUCCESS;
}
// Disable memory remapping and return to normal mapping // Disable memory remapping and return to normal mapping
MmioOr32 (SP810_CTRL_BASE, BIT8); MmioOr32 (SP810_CTRL_BASE, BIT8);
return RETURN_SUCCESS;
} }
/** /**

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@ -115,9 +115,9 @@ ArmPlatformSecExtraAction (
in the PEI phase. in the PEI phase.
**/ **/
VOID RETURN_STATUS
ArmPlatformNormalInitialize ( ArmPlatformInitialize (
VOID IN UINTN MpId
); );
/** /**

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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -92,12 +92,18 @@ ArmPlatformGetBootMode (
in the PEI phase. in the PEI phase.
**/ **/
VOID RETURN_STATUS
ArmPlatformNormalInitialize ( ArmPlatformInitialize (
VOID IN UINTN MpId
) )
{ {
if (!IS_PRIMARY_CORE(MpId)) {
return RETURN_SUCCESS;
}
//TODO: Implement me //TODO: Implement me
return RETURN_SUCCESS;
} }
/** /**

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@ -1,5 +1,5 @@
#/* @file #/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011-2012, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
@ -36,3 +36,6 @@
[FixedPcd] [FixedPcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdSystemMemorySize
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -24,9 +24,6 @@ PlatformPeim (
VOID VOID
) )
{ {
// Initialize the platform specific controllers
ArmPlatformNormalInitialize ();
BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize)); BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize));
return EFI_SUCCESS; return EFI_SUCCESS;

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@ -1,6 +1,6 @@
#/** @file #/** @file
# #
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011-2012, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License

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@ -1,6 +1,6 @@
#/** @file #/** @file
# #
# Copyright (c) 2011, ARM Limited. All rights reserved. # Copyright (c) 2011-2012, ARM Limited. All rights reserved.
# #
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License

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@ -100,6 +100,9 @@ CEntryPoint (
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL); InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
SaveAndSetDebugTimerInterrupt (TRUE); SaveAndSetDebugTimerInterrupt (TRUE);
// Initialize the platform specific controllers
ArmPlatformInitialize (MpId);
// Goto primary Main. // Goto primary Main.
PrimaryMain (PeiCoreEntryPoint); PrimaryMain (PeiCoreEntryPoint);
} else { } else {

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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -175,6 +175,9 @@ CEntryPoint (
{ {
UINT64 StartTimeStamp; UINT64 StartTimeStamp;
// Initialize the platform specific controllers
ArmPlatformInitialize (MpId);
if (IS_PRIMARY_CORE(MpId) && PerformanceMeasurementEnabled ()) { if (IS_PRIMARY_CORE(MpId) && PerformanceMeasurementEnabled ()) {
// Initialize the Timer Library to setup the Timer HW controller // Initialize the Timer Library to setup the Timer HW controller
TimerConstructor (); TimerConstructor ();

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@ -1,6 +1,6 @@
/** @file /** @file
* *
* Copyright (c) 2011, ARM Limited. All rights reserved. * Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* *
* This program and the accompanying materials * This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License * are licensed and made available under the terms and conditions of the BSD License
@ -110,9 +110,9 @@ ArmPlatformGetBootMode (
For example, some L2x0 requires to be initialized in Secure World For example, some L2x0 requires to be initialized in Secure World
**/ **/
VOID RETURN_STATUS
ArmPlatformNormalInitialize ( ArmPlatformInitialize (
VOID IN UINTN MpId
) )
{ {
BEAGLEBOARD_REVISION Revision; BEAGLEBOARD_REVISION Revision;
@ -132,6 +132,8 @@ ArmPlatformNormalInitialize (
// Clear IRQs // Clear IRQs
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSyncronizationBarrier (); ArmDataSyncronizationBarrier ();
return RETURN_SUCCESS;
} }
/** /**