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UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150

v4:
The v3 posting didn't do what it promised to do, so do it now for real.

V3 changes:
change to mov instruction (non locking instuction) instead
of xchg to simplify design.

V2 changes:
Add xchg 16 bit instructions to handle sgdt and sidt base
63:48 bits and 47:32 bits.
Add comment to explain why xchg 64bit isnt being used

Split lock happens when a locking instruction is used on mis-aligned data
that crosses two cachelines. If close source platform enables Alignment
Check Exception(#AC), They can hit a double fault due to split lock being
in CpuExceptionHandlerLib.

sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit.
The data is mis-aligned, can cross two cacheline, and a xchg
instruction(locking instuction) is being utilize.

Signed-off-by: John E Lofgren <john.e.lofgren@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
John E Lofgren 2019-09-18 23:43:23 +08:00 committed by Eric Dong
parent 832c4c7ad6
commit f4c898f2b2
1 changed files with 8 additions and 6 deletions
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14
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
View File

@ -184,17 +184,19 @@ HasErrorCode:
push rax
push rax
sidt [rsp]
xchg rax, [rsp + 2]
xchg rax, [rsp]
xchg rax, [rsp + 8]
mov bx, word [rsp]
mov rax, qword [rsp + 2]
mov qword [rsp], rax
mov word [rsp + 8], bx
xor rax, rax
push rax
push rax
sgdt [rsp]
xchg rax, [rsp + 2]
xchg rax, [rsp]
xchg rax, [rsp + 8]
mov bx, word [rsp]
mov rax, qword [rsp + 2]
mov qword [rsp], rax
mov word [rsp + 8], bx
;; UINT64 Ldtr, Tr;
xor rax, rax