mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicDxe
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15627 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
oliviermartin
parent
793ca69f50
commit
f5241b5725
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@ -1,8 +1,6 @@
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/*++
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Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
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Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -24,214 +22,8 @@ Abstract:
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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#include "ArmGicDxe.h"
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#define ARM_GIC_DEFAULT_PRIORITY 0x80
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
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/**
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Enable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt enabled.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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EnableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicEnableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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/**
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Disable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt disabled.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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DisableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicDisableInterrupt (PcdGet32(PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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/**
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Return current state of interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@param InterruptState TRUE: source enabled, FALSE: source disabled.
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@retval EFI_SUCCESS InterruptState is valid
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@retval EFI_DEVICE_ERROR InterruptState is not valid
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**/
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EFI_STATUS
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EFIAPI
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GetInterruptSourceState (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN BOOLEAN *InterruptState
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)
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{
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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*InterruptState = ArmGicIsInterruptEnabled (PcdGet32(PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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/**
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Signal to the hardware that the End Of Intrrupt state
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has been reached.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt EOI'ed.
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@retval EFI_DEVICE_ERROR Hardware could not be programmed.
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**/
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EFI_STATUS
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EFIAPI
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EndOfInterrupt (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicEndOfInterrupt (PcdGet32(PcdGicInterruptInterfaceBase), Source);
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return EFI_SUCCESS;
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}
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/**
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EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
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@param InterruptType Defines the type of interrupt or exception that
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occurred on the processor.This parameter is processor architecture specific.
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@param SystemContext A pointer to the processor context when
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the interrupt occurred on the processor.
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@return None
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**/
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VOID
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EFIAPI
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IrqInterruptHandler (
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IN EFI_EXCEPTION_TYPE InterruptType,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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UINT32 GicInterrupt;
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HARDWARE_INTERRUPT_HANDLER InterruptHandler;
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GicInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicInterruptInterfaceBase));
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// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
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if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
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// The special interrupt do not need to be acknowledge
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return;
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}
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InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
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if (InterruptHandler != NULL) {
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// Call the registered interrupt handler.
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InterruptHandler (GicInterrupt, SystemContext);
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} else {
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DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
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}
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EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);
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}
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//
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// The protocol instance produced by this driver
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//
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EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
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RegisterInterruptSource,
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EnableInterruptSource,
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DisableInterruptSource,
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GetInterruptSourceState,
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EndOfInterrupt
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};
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/**
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Shutdown our hardware
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DXE Core will disable interrupts and turn off the timer and disable interrupts
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after all the event handlers have run.
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@param[in] Event The Event that is being processed
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@param[in] Context Event Context
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**/
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VOID
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EFIAPI
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ExitBootServicesEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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UINTN Index;
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// Acknowledge all pending interrupts
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for (Index = 0; Index < mGicNumInterrupts; Index++) {
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DisableInterruptSource (&gHardwareInterruptProtocol, Index);
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}
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for (Index = 0; Index < mGicNumInterrupts; Index++) {
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EndOfInterrupt (&gHardwareInterruptProtocol, Index);
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}
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// Disable Gic Interface
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ArmGicDisableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// Disable Gic Distributor
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ArmGicDisableDistributor (PcdGet32(PcdGicDistributorBase));
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}
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/**
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Initialize the state information for the CPU Architectural Protocol
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@ -249,66 +41,9 @@ InterruptDxeInitialize (
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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UINT32 RegOffset;
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UINTN RegShift;
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UINT32 CpuTarget;
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// Make sure the Interrupt Controller Protocol is not already installed in the system.
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ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
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EFI_STATUS Status;
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mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
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for (Index = 0; Index < mGicNumInterrupts; Index++) {
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DisableInterruptSource (&gHardwareInterruptProtocol, Index);
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// Set Priority
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RegOffset = Index / 4;
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RegShift = (Index % 4) * 8;
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MmioAndThenOr32 (
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PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
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~(0xff << RegShift),
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ARM_GIC_DEFAULT_PRIORITY << RegShift
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);
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}
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//
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// Targets the interrupts to the Primary Cpu
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//
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// Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
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// the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
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// connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
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// More Info in the GIC Specification about "Interrupt Processor Targets Registers"
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//
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// Read the first Interrupt Processor Targets Register (that corresponds to the 4
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// first SGIs)
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CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
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// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
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// is 0 when we run on a uniprocessor platform.
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if (CpuTarget != 0) {
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// The 8 first Interrupt Processor Targets Registers are read-only
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for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
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MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
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}
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}
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// Set binary point reg to 0x7 (no preemption)
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
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// Set priority mask reg to 0xff to allow all priorities through
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
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// Enable gic cpu interface
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ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
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// Enable gic distributor
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ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
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Status = InstallAndRegisterInterruptService (
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&gHardwareInterruptProtocol, IrqInterruptHandler, ExitBootServicesEvent);
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Status = GicV2DxeInitialize (ImageHandle, SystemTable);
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return Status;
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}
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@ -15,8 +15,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#ifndef __ARM_GIC_DXE_H__
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#define __ARM_GIC_DXE_H__
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#include <Library/ArmGicLib.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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@ -44,4 +46,13 @@ RegisterInterruptSource (
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IN HARDWARE_INTERRUPT_HANDLER Handler
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);
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//
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// GicV2 API
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//
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EFI_STATUS
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GicV2DxeInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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);
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#endif
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@ -26,6 +26,8 @@
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ArmGicDxe.c
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ArmGicCommonDxe.c
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GicV2/ArmGicV2Dxe.c
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[Packages]
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MdePkg/MdePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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@ -45,11 +47,11 @@
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[Protocols]
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gHardwareInterruptProtocolGuid
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gEfiCpuArchProtocolGuid
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[FixedPcd.common]
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
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gArmTokenSpaceGuid.PcdArmPrimaryCore
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[Depex]
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@ -0,0 +1,312 @@
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/*++
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Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
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Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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GicV2/ArmGicV2Dxe.c
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Abstract:
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Driver implementing the GicV2 interrupt controller protocol
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--*/
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#include "ArmGicDxe.h"
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#include "GicV2/ArmGicV2Lib.h"
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#define ARM_GIC_DEFAULT_PRIORITY 0x80
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
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/**
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Enable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt enabled.
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@retval EFI_UNSUPPORTED Source interrupt is not supported
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**/
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EFI_STATUS
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EFIAPI
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GicV2EnableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicEnableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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/**
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Disable interrupt source Source.
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@param This Instance pointer for this protocol
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@param Source Hardware source of the interrupt
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@retval EFI_SUCCESS Source interrupt disabled.
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@retval EFI_UNSUPPORTED Source interrupt is not supported
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**/
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EFI_STATUS
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EFIAPI
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GicV2DisableInterruptSource (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
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)
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{
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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ArmGicDisableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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/**
|
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Return current state of interrupt source Source.
|
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|
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@param This Instance pointer for this protocol
|
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@param Source Hardware source of the interrupt
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@param InterruptState TRUE: source enabled, FALSE: source disabled.
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@retval EFI_SUCCESS InterruptState is valid
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@retval EFI_UNSUPPORTED Source interrupt is not supported
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**/
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EFI_STATUS
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EFIAPI
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GicV2GetInterruptSourceState (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN BOOLEAN *InterruptState
|
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)
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{
|
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if (Source > mGicNumInterrupts) {
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ASSERT(FALSE);
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return EFI_UNSUPPORTED;
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}
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*InterruptState = ArmGicIsInterruptEnabled (FixedPcdGet32 (PcdGicDistributorBase), Source);
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return EFI_SUCCESS;
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}
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|
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/**
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Signal to the hardware that the End Of Interrupt state
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has been reached.
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@param This Instance pointer for this protocol
|
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@param Source Hardware source of the interrupt
|
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@retval EFI_SUCCESS Source interrupt EOI'ed.
|
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@retval EFI_UNSUPPORTED Source interrupt is not supported
|
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|
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**/
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EFI_STATUS
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EFIAPI
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GicV2EndOfInterrupt (
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IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
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IN HARDWARE_INTERRUPT_SOURCE Source
|
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)
|
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{
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if (Source > mGicNumInterrupts) {
|
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ASSERT(FALSE);
|
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return EFI_UNSUPPORTED;
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}
|
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|
||||
ArmGicV2EndOfInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase), Source);
|
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return EFI_SUCCESS;
|
||||
}
|
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|
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/**
|
||||
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
|
||||
|
||||
@param InterruptType Defines the type of interrupt or exception that
|
||||
occurred on the processor.This parameter is processor architecture specific.
|
||||
@param SystemContext A pointer to the processor context when
|
||||
the interrupt occurred on the processor.
|
||||
|
||||
@return None
|
||||
|
||||
**/
|
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VOID
|
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EFIAPI
|
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GicV2IrqInterruptHandler (
|
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IN EFI_EXCEPTION_TYPE InterruptType,
|
||||
IN EFI_SYSTEM_CONTEXT SystemContext
|
||||
)
|
||||
{
|
||||
UINT32 GicInterrupt;
|
||||
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
|
||||
|
||||
GicInterrupt = ArmGicV2AcknowledgeInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
|
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|
||||
// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
|
||||
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
|
||||
// The special interrupt do not need to be acknowledge
|
||||
return;
|
||||
}
|
||||
|
||||
InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
|
||||
if (InterruptHandler != NULL) {
|
||||
// Call the registered interrupt handler.
|
||||
InterruptHandler (GicInterrupt, SystemContext);
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
|
||||
}
|
||||
|
||||
GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
|
||||
}
|
||||
|
||||
//
|
||||
// The protocol instance produced by this driver
|
||||
//
|
||||
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
|
||||
RegisterInterruptSource,
|
||||
GicV2EnableInterruptSource,
|
||||
GicV2DisableInterruptSource,
|
||||
GicV2GetInterruptSourceState,
|
||||
GicV2EndOfInterrupt
|
||||
};
|
||||
|
||||
/**
|
||||
Shutdown our hardware
|
||||
|
||||
DXE Core will disable interrupts and turn off the timer and disable interrupts
|
||||
after all the event handlers have run.
|
||||
|
||||
@param[in] Event The Event that is being processed
|
||||
@param[in] Context Event Context
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
GicV2ExitBootServicesEvent (
|
||||
IN EFI_EVENT Event,
|
||||
IN VOID *Context
|
||||
)
|
||||
{
|
||||
UINTN Index;
|
||||
UINT32 GicInterrupt;
|
||||
|
||||
// Disable all the interrupts
|
||||
for (Index = 0; Index < mGicNumInterrupts; Index++) {
|
||||
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
|
||||
}
|
||||
|
||||
// Acknowledge all pending interrupts
|
||||
do {
|
||||
GicInterrupt = ArmGicV2AcknowledgeInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
|
||||
|
||||
if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {
|
||||
GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
|
||||
}
|
||||
} while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));
|
||||
|
||||
// Disable Gic Interface
|
||||
ArmGicV2DisableInterruptInterface (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
|
||||
|
||||
// Disable Gic Distributor
|
||||
ArmGicDisableDistributor (FixedPcdGet32 (PcdGicDistributorBase));
|
||||
}
|
||||
|
||||
/**
|
||||
Initialize the state information for the CPU Architectural Protocol
|
||||
|
||||
@param ImageHandle of the loaded driver
|
||||
@param SystemTable Pointer to the System Table
|
||||
|
||||
@retval EFI_SUCCESS Protocol registered
|
||||
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
|
||||
@retval EFI_DEVICE_ERROR Hardware problems
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
GicV2DxeInitialize (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINTN Index;
|
||||
UINT32 RegOffset;
|
||||
UINTN RegShift;
|
||||
UINT32 CpuTarget;
|
||||
|
||||
// Make sure the Interrupt Controller Protocol is not already installed in the system.
|
||||
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
|
||||
|
||||
mGicNumInterrupts = ArmGicGetMaxNumInterrupts (FixedPcdGet32 (PcdGicDistributorBase));
|
||||
|
||||
for (Index = 0; Index < mGicNumInterrupts; Index++) {
|
||||
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
|
||||
|
||||
// Set Priority
|
||||
RegOffset = Index / 4;
|
||||
RegShift = (Index % 4) * 8;
|
||||
MmioAndThenOr32 (
|
||||
FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4 * RegOffset),
|
||||
~(0xff << RegShift),
|
||||
ARM_GIC_DEFAULT_PRIORITY << RegShift
|
||||
);
|
||||
}
|
||||
|
||||
//
|
||||
// Targets the interrupts to the Primary Cpu
|
||||
//
|
||||
|
||||
// Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
|
||||
// the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
|
||||
// connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
|
||||
// More Info in the GIC Specification about "Interrupt Processor Targets Registers"
|
||||
//
|
||||
// Read the first Interrupt Processor Targets Register (that corresponds to the 4
|
||||
// first SGIs)
|
||||
CpuTarget = MmioRead32 (FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
|
||||
|
||||
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
|
||||
// is 0 when we run on a uniprocessor platform.
|
||||
if (CpuTarget != 0) {
|
||||
// The 8 first Interrupt Processor Targets Registers are read-only
|
||||
for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
|
||||
MmioWrite32 (FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
|
||||
}
|
||||
}
|
||||
|
||||
// Set binary point reg to 0x7 (no preemption)
|
||||
MmioWrite32 (FixedPcdGet32 (PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
|
||||
|
||||
// Set priority mask reg to 0xff to allow all priorities through
|
||||
MmioWrite32 (FixedPcdGet32 (PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
|
||||
|
||||
// Enable gic cpu interface
|
||||
ArmGicEnableInterruptInterface (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
|
||||
|
||||
// Enable gic distributor
|
||||
ArmGicEnableDistributor (FixedPcdGet32 (PcdGicDistributorBase));
|
||||
|
||||
Status = InstallAndRegisterInterruptService (
|
||||
&gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);
|
||||
|
||||
return Status;
|
||||
}
|
||||
Loading…
Reference in New Issue