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MdeModulePkg/SdMmcOverride: Add GetOperatingParam notify phase 

https://bugzilla.tianocore.org/show_bug.cgi?id=1882

The new notify phase allows platform to configure additional
bus parameters in addition to parameters that can already be configured
with capability override. Specifically we allow to configure bus width,
clock frequency and driver strength. If platform doesn't wish to configure
some of the parameters it can left it on default values and driver will
assume it's standard behavior with respect to those parameters.
The definition of the SD_MMC_BUS_MODE has been extended to
incorporate SD card default speed and high speed.

Tests on Marvell boards were also performed by Marcin Wojtas
<mw@semihalf.com>:

https://edk2.groups.io/g/devel/message/42999

Board 1 (out of tree): SD - OK, MMC - OK
Board 2: (Armada80x0McBin): SD - OK, MMC - OK
Board 3: (Armada70x0Db): SD - problems, MMC - OK

Please note that the problem on Armada70x0Db SD devices are introduced by
adding new types of SD bus modes, a subsequent patch within edk2-platforms
repository will be proposed to address it.
(More details can be referred from the above link.)

Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Regression-tested-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Albecki, Mateusz 2019-06-26 21:10:02 +08:00 committed by Hao A Wu
parent a37e18f6fc
commit f56cc67f62
1 changed files with 53 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
MdeModulePkg/Include/Protocol/SdMmcOverride.h
View File

@ -16,19 +16,66 @@
#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
{ 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } }
#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x2
#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x3
typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE;
//
// Bus timing modes
//
#define EDKII_SD_MMC_BUS_WIDTH_IGNORE MAX_UINT8
#define EDKII_SD_MMC_CLOCK_FREQ_IGNORE MAX_UINT32
#define EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE MAX_UINT8
typedef enum {
SdDriverStrengthTypeB = 0,
SdDriverStrengthTypeA,
SdDriverStrengthTypeC,
SdDriverStrengthTypeD,
SdDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE
} SD_DRIVER_STRENGTH_TYPE;
typedef enum {
EmmcDriverStrengthType0 = 0,
EmmcDriverStrengthType1,
EmmcDriverStrengthType2,
EmmcDriverStrengthType3,
EmmcDriverStrengthType4,
EmmcDriverStrengthIgnore = EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE
} EMMC_DRIVER_STRENGTH_TYPE;
typedef union {
SD_DRIVER_STRENGTH_TYPE Sd;
EMMC_DRIVER_STRENGTH_TYPE Emmc;
} EDKII_SD_MMC_DRIVER_STRENGTH;
typedef struct {
//
// The target width of the bus. If user tells driver to ignore it
// or specifies unsupported width driver will choose highest supported
// bus width for a given mode.
//
UINT8 BusWidth;
//
// The target clock frequency of the bus in MHz. If user tells driver to ignore
// it or specifies unsupported frequency driver will choose highest supported
// clock frequency for a given mode.
//
UINT32 ClockFreq;
//
// The target driver strength of the bus. If user tells driver to
// ignore it or specifies unsupported driver strength, driver will
// default to Type0 for eMMC cards and TypeB for SD cards. Driver strength
// setting is only considered if chosen bus timing supports them.
//
EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength;
} EDKII_SD_MMC_OPERATING_PARAMETERS;
typedef enum {
SdMmcSdDs,
SdMmcSdHs,
SdMmcUhsSdr12,
SdMmcUhsSdr25,
SdMmcUhsSdr50,
SdMmcUhsSdr104,
SdMmcUhsDdr50,
SdMmcUhsSdr104,
SdMmcMmcLegacy,
SdMmcMmcHsSdr,
SdMmcMmcHsDdr,
@ -43,10 +90,10 @@ typedef enum {
EdkiiSdMmcInitHostPost,
EdkiiSdMmcUhsSignaling,
EdkiiSdMmcSwitchClockFreqPost,
EdkiiSdMmcGetOperatingParam
} EDKII_SD_MMC_PHASE_TYPE;
/**
Override function for SDHCI capability bits
@param[in] ControllerHandle The EFI_HANDLE of the controller.
@ -70,7 +117,6 @@ EFI_STATUS
);
/**
Override function for SDHCI controller operations
@param[in] ControllerHandle The EFI_HANDLE of the controller.