diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf index 97b206d780..185c0ae406 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf @@ -42,5 +42,3 @@ gArmPlatformTokenSpaceGuid.PcdStandalone [FixedPcd] - gArmTokenSpaceGuid.PcdNormalFdBaseAddress - gArmTokenSpaceGuid.PcdNormalFdSize diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c index 95fd2bb484..616fa0ef8c 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c @@ -18,6 +18,8 @@ #include #include +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 + // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED @@ -34,76 +36,84 @@ entry **/ -VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) { - UINT32 CacheAttributes; - BOOLEAN bTrustzoneSupport = FALSE; - UINTN Index = 0; - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINT32 CacheAttributes; + BOOLEAN bTrustzoneSupport = FALSE; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; - ASSERT(VirtualMemoryMap != NULL); + ASSERT(VirtualMemoryMap != NULL); - VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9); - if (VirtualMemoryTable == NULL) { - return; - } + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { - CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED); - } else { - CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED); - } + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED); + } else { + CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED); + } - // ReMap (Either NOR Flash or DRAM) - VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_EB_REMAP_BASE; - VirtualMemoryTable[Index].Length = ARM_EB_REMAP_SZ; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; + // ReMap (Either NOR Flash or DRAM) + VirtualMemoryTable[Index].PhysicalBase = ARM_EB_REMAP_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_EB_REMAP_BASE; + VirtualMemoryTable[Index].Length = ARM_EB_REMAP_SZ; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; - // DDR - VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_DRAM_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_EB_DRAM_BASE; - VirtualMemoryTable[Index].Length = ARM_EB_DRAM_SZ; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; + // DDR + VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_DRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_EB_DRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_EB_DRAM_SZ; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; - // SMC CS7 - VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE; - VirtualMemoryTable[Index].Length = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); + // SMC CS7 + VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); - // SMB CS0-CS1 - NOR Flash 1 & 2 - VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_NOR_BASE; - VirtualMemoryTable[Index].Length = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ; - VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); + // SMB CS0-CS1 - NOR Flash 1 & 2 + VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_NOR_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_NOR_BASE; + VirtualMemoryTable[Index].Length = ARM_EB_SMB_NOR_SZ + ARM_EB_SMB_DOC_SZ; + VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); - // SMB CS2 - SRAM - VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_SRAM_BASE; - VirtualMemoryTable[Index].Length = ARM_EB_SMB_SRAM_SZ; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; + // SMB CS2 - SRAM + VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_SRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_EB_SMB_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; - // SMB CS3-CS6 - Motherboard Peripherals - VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_PERIPH_BASE; - VirtualMemoryTable[Index].Length = ARM_EB_SMB_PERIPH_SZ; - VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); + // SMB CS3-CS6 - Motherboard Peripherals + VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_EB_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_EB_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); - // If a Logic Tile is connected to The ARM Versatile Express Motherboard - if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) { - VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE; - VirtualMemoryTable[Index].VirtualBase = ARM_EB_LOGIC_TILE_BASE; - VirtualMemoryTable[Index].Length = ARM_EB_LOGIC_TILE_SZ; - VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); - } + // If a Logic Tile is connected to The ARM Versatile Express Motherboard + if (MmioRead32(ARM_EB_SYS_PROCID1_REG) != 0) { + VirtualMemoryTable[++Index].PhysicalBase = ARM_EB_LOGIC_TILE_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_EB_LOGIC_TILE_BASE; + VirtualMemoryTable[Index].Length = ARM_EB_LOGIC_TILE_SZ; + VirtualMemoryTable[Index].Attributes = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE); - // End of Table - VirtualMemoryTable[++Index].PhysicalBase = 0; - VirtualMemoryTable[Index].VirtualBase = 0; - VirtualMemoryTable[Index].Length = 0; - VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1)); + } else { + ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + } - *VirtualMemoryMap = VirtualMemoryTable; + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + *VirtualMemoryMap = VirtualMemoryTable; } /** @@ -118,7 +128,8 @@ VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemory **/ EFI_STATUS ArmPlatformGetAdditionalSystemMemory ( - OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap -) { + OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap + ) +{ return EFI_UNSUPPORTED; } diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf index e5bb73d9e3..fe05824bca 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSecLib.inf @@ -42,5 +42,3 @@ gArmPlatformTokenSpaceGuid.PcdStandalone [FixedPcd] - gArmTokenSpaceGuid.PcdNormalFdBaseAddress - gArmTokenSpaceGuid.PcdNormalFdSize diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf index a6186b5e7e..4c8f6c0260 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf @@ -47,7 +47,4 @@ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping [FixedPcd] - gArmTokenSpaceGuid.PcdNormalFdBaseAddress - gArmTokenSpaceGuid.PcdNormalFdSize - gArmTokenSpaceGuid.PcdL2x0ControllerBase diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf index c0af6940c5..cf4e68ebc0 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf @@ -48,7 +48,4 @@ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping [FixedPcd] - gArmTokenSpaceGuid.PcdNormalFdBaseAddress - gArmTokenSpaceGuid.PcdNormalFdSize - gArmTokenSpaceGuid.PcdL2x0ControllerBase diff --git a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h index 3fec90298c..26e79923d3 100644 --- a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h @@ -158,21 +158,6 @@ ArmPlatformTrustzoneInit ( VOID ); -/** - Return the information about the memory region in permanent memory used by PEI - - One of the PEI Module must install the permament memory used by PEI. This function returns the - information about this region for your platform to this PEIM module. - - @param[out] PeiMemoryBase Base of the memory region used by PEI core and modules - @param[out] PeiMemorySize Size of the memory region used by PEI core and modules - -**/ -VOID ArmPlatformGetPeiMemory ( - OUT UINTN* PeiMemoryBase, - OUT UINTN* PeiMemorySize - ); - /** Return the Virtual Memory Map of your platform diff --git a/ArmPlatformPkg/MemoryInitPei/MemoryInit.c b/ArmPlatformPkg/MemoryInitPei/MemoryInit.c index e616c075e1..4b31de96b1 100644 --- a/ArmPlatformPkg/MemoryInitPei/MemoryInit.c +++ b/ArmPlatformPkg/MemoryInitPei/MemoryInit.c @@ -16,6 +16,7 @@ // The package level header files this module uses // #include + // // The protocols, PPI and GUID defintions for this module // @@ -35,28 +36,24 @@ #include #include -// -// Module globals -// - VOID InitMmu ( VOID ) { - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; - VOID *TranslationTableBase; - UINTN TranslationTableSize; + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + VOID *TranslationTableBase; + UINTN TranslationTableSize; - // Get Virtual Memory Map from the Platform Library - ArmPlatformGetVirtualMemoryMap(&MemoryTable); + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap(&MemoryTable); - //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in - // DRAM (even at the top of DRAM as it is the first permanent memory allocation) - ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize); + //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in + // DRAM (even at the top of DRAM as it is the first permanent memory allocation) + ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize); } -// May want to put this into a library so you only need the PCD setings if you are using the feature? +// May want to put this into a library so you only need the PCD settings if you are using the feature? VOID BuildMemoryTypeInformationHob ( VOID @@ -87,10 +84,8 @@ BuildMemoryTypeInformationHob ( Info[9].Type = EfiMaxMemoryType; Info[9].NumberOfPages = 0; - BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, &Info, sizeof (Info)); } - /*++ Routine Description: @@ -234,7 +229,7 @@ InitializeMemory ( InitMmu (); if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { - // Optional feature that helps prevent EFI memory map fragmentation. + // Optional feature that helps prevent EFI memory map fragmentation. BuildMemoryTypeInformationHob (); } diff --git a/ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf b/ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf index 87ea168db3..058a635bbe 100644 --- a/ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf +++ b/ArmPlatformPkg/MemoryInitPei/MemoryInitPei.inf @@ -1,6 +1,6 @@ #/** @file # -# Copyright (c) 2010, ARM Ltd. All rights reserved.
+# Copyright (c) 2011, ARM Ltd. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License # which accompanies this distribution. The full text of the license may be found at diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index 2e6477d550..39de31a42a 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -12,13 +12,14 @@ * **/ -#include #include #include #include #include #include +#include "PrePeiCore.h" + extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; /* @@ -32,60 +33,64 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; */ VOID EFIAPI -secondary_main(IN UINTN CoreId) +SecondaryMain ( + IN UINTN CoreId + ) { - //Function pointer to Secondary Core entry point - VOID (*secondary_start)(VOID); - UINTN secondary_entry_addr=0; + // Function pointer to Secondary Core entry point + VOID (*secondary_start)(VOID); + UINTN secondary_entry_addr=0; - //Clear Secondary cores MailBox - ArmClearMPCoreMailbox(); + // Clear Secondary cores MailBox + ArmClearMPCoreMailbox(); - while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) { - ArmCallWFI(); - //Acknowledge the interrupt and send End of Interrupt signal. - PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/); - } + while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) { + ArmCallWFI(); + // Acknowledge the interrupt and send End of Interrupt signal. + PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/); + } - secondary_start = (VOID (*)())secondary_entry_addr; + secondary_start = (VOID (*)())secondary_entry_addr; - //Jump to secondary core entry point. - secondary_start(); + // Jump to secondary core entry point. + secondary_start(); - //the secondaries shouldn't reach here - ASSERT(FALSE); + // The secondaries shouldn't reach here + ASSERT(FALSE); } -VOID primary_main ( +VOID +EFIAPI +PrimaryMain ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { - EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_SEC_PEI_HAND_OFF SecCoreData; - //Enable the GIC Distributor - PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase)); + //Enable the GIC Distributor + PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase)); - // If ArmVe has not been built as Standalone then we need to wake up the secondary cores - if (FeaturePcdGet(PcdStandalone) == FALSE) { - // Sending SGI to all the Secondary CPU interfaces - PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); - } + // If ArmVe has not been built as Standalone then we need to wake up the secondary cores + if (FeaturePcdGet(PcdStandalone) == FALSE) { + // Sending SGI to all the Secondary CPU interfaces + PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); + } - // - // Bind this information into the SEC hand-off state - // Note: this must be in sync with the stuff in the asm file - // Note also: HOBs (pei temp ram) MUST be above stack - // - SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); - SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); - SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) - SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); - SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); - SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; - SecCoreData.StackBase = SecCoreData.TemporaryRamBase; - SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; + // + // Bind this information into the SEC hand-off state + // Note: this must be in sync with the stuff in the asm file + // Note also: HOBs (pei temp ram) MUST be above stack + // + SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); + SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) + SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); + SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); + SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; + SecCoreData.StackBase = SecCoreData.TemporaryRamBase; + SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; - // jump to pei core entry point - (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); + // Jump to PEI core entry point + (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); } diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c index 15e7629c86..c09494557b 100644 --- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c @@ -12,42 +12,47 @@ * **/ -#include #include #include #include +#include "PrePeiCore.h" + extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable; VOID EFIAPI -secondary_main(IN UINTN CoreId) +SecondaryMain ( + IN UINTN CoreId + ) { - ASSERT(FALSE); + ASSERT(FALSE); } -VOID primary_main ( +VOID +EFIAPI +PrimaryMain ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { - EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_SEC_PEI_HAND_OFF SecCoreData; - // - // Bind this information into the SEC hand-off state - // Note: this must be in sync with the stuff in the asm file - // Note also: HOBs (pei temp ram) MUST be above stack - // - SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); - SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); - SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) - SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); - SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); - SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; - SecCoreData.StackBase = SecCoreData.TemporaryRamBase; - SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; + // + // Bind this information into the SEC hand-off state + // Note: this must be in sync with the stuff in the asm file + // Note also: HOBs (pei temp ram) MUST be above stack + // + SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress); + SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize); + SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack) + SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize); + SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2)); + SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2; + SecCoreData.StackBase = SecCoreData.TemporaryRamBase; + SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize; - // jump to pei core entry point - (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); + // jump to pei core entry point + (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable); } diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index f76a1b191f..56186471fa 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -13,29 +13,17 @@ * **/ -#include -#include #include #include #include #include #include +#include #include +#include #include -EFI_STATUS -EFIAPI -SecTemporaryRamSupport ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, - IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, - IN UINTN CopySize - ); - -VOID -SecSwitchStack ( - INTN StackDelta - ); +#include "PrePeiCore.h" EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport}; @@ -47,10 +35,6 @@ EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = { } }; -// Vector Table for Pei Phase -VOID PeiVectorTable (VOID); - - VOID CEntryPoint ( IN UINTN CoreId, @@ -64,8 +48,8 @@ CEntryPoint ( ArmInvalidateInstructionCache(); // Enable Instruction & Data caches - ArmEnableDataCache(); - ArmEnableInstructionCache(); + ArmEnableDataCache (); + ArmEnableInstructionCache (); // // Note: Doesn't have to Enable CPU interface in non-secure world, @@ -81,9 +65,9 @@ CEntryPoint ( //If not primary Jump to Secondary Main if(0 == CoreId) { //Goto primary Main. - primary_main(PeiCoreEntryPoint); + PrimaryMain (PeiCoreEntryPoint); } else { - secondary_main(CoreId); + SecondaryMain (CoreId); } // PEI Core should always load and never return @@ -101,7 +85,7 @@ SecTemporaryRamSupport ( { // // Migrate the whole temporary memory to permenent memory. - // + // CopyMem ( (VOID*)(UINTN)PermanentMemoryBase, (VOID*)(UINTN)TemporaryMemoryBase, diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h new file mode 100644 index 0000000000..0f8778c154 --- /dev/null +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h @@ -0,0 +1,60 @@ +/** @file +* Main file supporting the transition to PEI Core in Normal World for Versatile Express +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +#ifndef __PREPEICORE_H_ +#define __PREPEICORE_H_ + +#include +#include + + +EFI_STATUS +EFIAPI +SecTemporaryRamSupport ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +VOID +SecSwitchStack ( + INTN StackDelta + ); + +// Vector Table for Pei Phase +VOID PeiVectorTable (VOID); + +VOID +EFIAPI +PrimaryMain ( + IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint + ); + +/* + * This is the main function for secondary cores. They loop around until a non Null value is written to + * SYS_FLAGS register.The SYS_FLAGS register is platform specific. + * Note:The secondary cores, while executing secondary_main, assumes that: + * : SGI 0 is configured as Non-secure interrupt + * : Priority Mask is configured to allow SGI 0 + * : Interrupt Distributor and CPU interfaces are enabled + * + */ +VOID +EFIAPI +SecondaryMain ( + IN UINTN CoreId + ); + +#endif