mirror of https://github.com/acidanthera/audk.git
Remove IO and MMIO GCD add operations from this generic PCI Hot Bridge drivers.
A platform specific PEIm or DXE module is required to add the IO and MMIO resources to the GCD. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10658 6f19259b-4bc3-4df7-8a09-765794883524
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@ -14,17 +14,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#include "PciHostBridge.h"
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//
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// Support 64 K IO space
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//
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#define RES_IO_BASE 0x1000
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#define RES_IO_LIMIT 0xFFFF
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//
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// Support 4G address space
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//
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#define RES_MEM_BASE_1 0xF8000000
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#define RES_MEM_LIMIT_1 (0xFEC00000 - 1)
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//
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// Hard code: Root Bridge Number within the host bridge
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// Root Bridge's attribute
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@ -100,8 +89,6 @@ InitializePciHostBridge (
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UINTN Loop2;
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PCI_HOST_BRIDGE_INSTANCE *HostBridge;
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PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
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IN EFI_PHYSICAL_ADDRESS BaseAddress;
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IN UINT64 Length;
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mDriverImageHandle = ImageHandle;
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@ -162,29 +149,6 @@ InitializePciHostBridge (
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}
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}
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Status = gDS->AddIoSpace (
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EfiGcdIoTypeIo,
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RES_IO_BASE,
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RES_IO_LIMIT - RES_IO_BASE + 1
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);
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// PCI memory space from 3.75Gbytes->(4GBytes - BIOSFWH local APIC etc)
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Status = gDS->AddMemorySpace (
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EfiGcdMemoryTypeMemoryMappedIo,
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RES_MEM_BASE_1,
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(RES_MEM_LIMIT_1 - RES_MEM_BASE_1 + 1),
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0
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);
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BaseAddress = 0x80000000;
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Length = RES_MEM_BASE_1 - BaseAddress;
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Status = gDS->AddMemorySpace (
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EfiGcdMemoryTypeMemoryMappedIo,
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BaseAddress,
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Length,
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0
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);
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return EFI_SUCCESS;
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}
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