mirror of https://github.com/acidanthera/audk.git
Added support for L2 (4K) page tables and made the CPU driver change cachability attributes on request. Also got the DebugUncache infrastructure working for the first time. Looks like it works for the simple case. Checking in so we can get more eyes looking at the code.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
AJFISH
parent
66b631f5e0
commit
f659880bfa
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@ -49,6 +49,7 @@
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DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
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ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
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CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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[LibraryClasses.ARM]
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#
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@ -16,6 +16,34 @@
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BOOLEAN mInterruptState = FALSE;
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/**
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This function flushes the range of addresses from Start to Start+Length
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from the processor's data cache. If Start is not aligned to a cache line
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boundary, then the bytes before Start to the preceding cache line boundary
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are also flushed. If Start+Length is not aligned to a cache line boundary,
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then the bytes past Start+Length to the end of the next cache line boundary
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are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
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supported. If the data cache is fully coherent with all DMA operations, then
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this function can just return EFI_SUCCESS. If the processor does not support
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flushing a range of the data cache, then the entire data cache can be flushed.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param Start The beginning physical address to flush from the processor's data
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cache.
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@param Length The number of bytes to flush from the processor's data cache. This
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function may flush more bytes than Length specifies depending upon
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the granularity of the flush operation that the processor supports.
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@param FlushType Specifies the type of flush operation to perform.
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@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from
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the processor's data cache.
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@retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified
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by FlushType.
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@retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed
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from the processor's data cache.
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**/
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EFI_STATUS
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EFIAPI
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CpuFlushCpuDataCache (
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@ -25,6 +53,8 @@ CpuFlushCpuDataCache (
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IN EFI_CPU_FLUSH_TYPE FlushType
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)
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{
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DEBUG ((EFI_D_ERROR, "CpuFlushCpuDataCache (%lx, %lx, %x)\n", Start, Length, FlushType));
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switch (FlushType) {
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case EfiCpuFlushTypeWriteBack:
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WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
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@ -42,6 +72,16 @@ CpuFlushCpuDataCache (
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return EFI_SUCCESS;
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}
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/**
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This function enables interrupt processing by the processor.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS Interrupts are enabled on the processor.
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@retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.
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**/
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EFI_STATUS
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EFIAPI
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CpuEnableInterrupt (
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@ -55,6 +95,15 @@ CpuEnableInterrupt (
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}
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/**
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This function disables interrupt processing by the processor.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS Interrupts are disabled on the processor.
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@retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.
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**/
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EFI_STATUS
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EFIAPI
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CpuDisableInterrupt (
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@ -67,6 +116,20 @@ CpuDisableInterrupt (
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return EFI_SUCCESS;
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}
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/**
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This function retrieves the processor's current interrupt state a returns it in
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State. If interrupts are currently enabled, then TRUE is returned. If interrupts
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are currently disabled, then FALSE is returned.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param State A pointer to the processor's current interrupt state. Set to TRUE if
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interrupts are enabled and FALSE if interrupts are disabled.
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@retval EFI_SUCCESS The processor's current interrupt state was returned in State.
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@retval EFI_INVALID_PARAMETER State is NULL.
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**/
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EFI_STATUS
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EFIAPI
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CpuGetInterruptState (
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@ -82,6 +145,23 @@ CpuGetInterruptState (
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return EFI_SUCCESS;
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}
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/**
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This function generates an INIT on the processor. If this function succeeds, then the
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processor will be reset, and control will not be returned to the caller. If InitType is
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not supported by this processor, or the processor cannot programmatically generate an
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INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
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occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
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@param This The EFI_CPU_ARCH_PROTOCOL instance.
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@param InitType The type of processor INIT to perform.
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@retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.
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@retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported
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by this processor.
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@retval EFI_DEVICE_ERROR The processor INIT failed.
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**/
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EFI_STATUS
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EFIAPI
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CpuInit (
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@ -115,17 +195,6 @@ CpuGetTimerValue (
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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EFIAPI
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CpuSetMemoryAttributes (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes
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)
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{
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return EFI_UNSUPPORTED;
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}
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//
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// Globals used to initialize the protocol
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@ -149,8 +218,26 @@ CpuDxeInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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{
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EFI_STATUS Status;
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InitializeExceptions (&mCpu);
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return gBS->InstallMultipleProtocolInterfaces (&mCpuHandle, &gEfiCpuArchProtocolGuid, &mCpu, NULL);
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Status = gBS->InstallMultipleProtocolInterfaces (
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&mCpuHandle,
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&gEfiCpuArchProtocolGuid, &mCpu,
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&gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,
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NULL
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);
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//
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// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
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// and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go
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// after the protocol is installed
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//
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SyncCacheConfig (&mCpu);
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return Status;
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}
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@ -19,14 +19,29 @@
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#include <Library/ArmLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Library/PeCoffGetEntryPointLib.h>
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#include <Library/UefiLib.h>
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#include <Library/CpuLib.h>
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#include <Guid/DebugImageInfoTable.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/DebugSupport.h>
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#include <Protocol/DebugSupportPeriodicCallback.h>
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#include <Protocol/VirtualUncachedPages.h>
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#include <Protocol/LoadedImage.h>
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#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \
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EFI_MEMORY_WC | \
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EFI_MEMORY_WT | \
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EFI_MEMORY_WB | \
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EFI_MEMORY_UCE \
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)
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/**
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@ -83,9 +98,31 @@ RegisterDebuggerInterruptHandler (
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);
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EFI_STATUS
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EFIAPI
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CpuSetMemoryAttributes (
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IN EFI_CPU_ARCH_PROTOCOL *This,
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes
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);
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EFI_STATUS
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InitializeExceptions (
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IN EFI_CPU_ARCH_PROTOCOL *Cpu
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);
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EFI_STATUS
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SyncCacheConfig (
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IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
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);
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EFI_STATUS
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ConvertSectionToPages (
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IN EFI_PHYSICAL_ADDRESS BaseAddress
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);
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extern VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages;
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#endif // __CPU_DXE_ARM_EXCEPTION_H__
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@ -39,6 +39,7 @@
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#
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ExceptionSupport.ARMv6.asm | RVCT
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# ExceptionSupport.ARMv6.S | GCC
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Mmu.c
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[Packages]
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ArmPkg/ArmPkg.dec
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@ -50,10 +51,18 @@
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CacheMaintenanceLib
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UefiDriverEntryPoint
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ArmLib
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DxeServicesTableLib
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PeCoffGetEntryPointLib
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UefiLib
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CpuLib
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[Protocols]
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gEfiCpuArchProtocolGuid
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gEfiDebugSupportPeriodicCallbackProtocolGuid
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gVirtualUncachedPagesProtocolGuid
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[Guids]
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gEfiDebugImageInfoTableGuid
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[Pcd.common]
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
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@ -13,7 +13,8 @@
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**/
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#include "CpuDxe.h"
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#include <Library/CacheMaintenanceLib.h>
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EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *gDebugImageTableHeader = NULL;
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VOID
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ExceptionHandlersStart (
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@ -120,6 +121,76 @@ RegisterDebuggerInterruptHandler (
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return EFI_SUCCESS;
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}
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UINT32
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EFIAPI
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PeCoffGetSizeOfHeaders (
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IN VOID *Pe32Data
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)
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{
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EFI_IMAGE_DOS_HEADER *DosHdr;
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EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
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UINTN SizeOfHeaders;
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DosHdr = (EFI_IMAGE_DOS_HEADER *)Pe32Data;
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if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
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//
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// DOS image header is present, so read the PE header after the DOS image header.
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//
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Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN) Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));
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} else {
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//
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// DOS image header is not present, so PE header is at the image base.
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//
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Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
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}
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if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) {
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SizeOfHeaders = sizeof (EFI_TE_IMAGE_HEADER) + (UINTN)Hdr.Te->BaseOfCode - (UINTN)Hdr.Te->StrippedSize;
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} else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
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SizeOfHeaders = Hdr.Pe32->OptionalHeader.SizeOfHeaders;
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}
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return SizeOfHeaders;
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}
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CHAR8 *
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GetImageName (
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IN UINT32 FaultAddress,
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OUT UINT32 *ImageBase,
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OUT UINT32 *PeCoffSizeOfHeaders
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)
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{
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EFI_DEBUG_IMAGE_INFO *DebugTable;
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UINTN Entry;
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CHAR8 *Address;
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DebugTable = gDebugImageTableHeader->EfiDebugImageInfoTable;
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if (DebugTable == NULL) {
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return NULL;
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}
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Address = (CHAR8 *)(UINTN)FaultAddress;
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for (Entry = 0; Entry < gDebugImageTableHeader->TableSize; Entry++, DebugTable++) {
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if (DebugTable->NormalImage != NULL) {
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if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&
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(DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
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if ((Address >= DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
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(Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {
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*ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
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*PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
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return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
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}
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}
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}
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}
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return NULL;
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}
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CHAR8 *gExceptionTypeString[] = {
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"Reset",
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"Undefined Instruction",
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@ -174,11 +245,41 @@ CommonCExceptionHandler (
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}
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//
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// Code after here is the default exception handler...
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// Code after here is the default exception handler... Dump the context
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//
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DEBUG ((EFI_D_ERROR, "%a Exception from %08x\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC));
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ASSERT (FALSE);
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DEBUG ((EFI_D_ERROR, "\n%a Exception from instruction at 0x%08x CPSR 0x%08x\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR));
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DEBUG_CODE_BEGIN ();
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CHAR8 *Pdb;
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UINT32 ImageBase;
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UINT32 PeCoffSizeOfHeader;
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UINT32 Offset;
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Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);
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Offset = SystemContext.SystemContextArm->PC - ImageBase;
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if (Pdb != NULL) {
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DEBUG ((EFI_D_ERROR, "%a\n", Pdb));
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//
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// A PE/COFF image loads its headers into memory so the headers are
|
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// included in the linked addressess. ELF and Mach-O images do not
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// include the headers so the first byte of the image is usually
|
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// text (code). If you look at link maps from ELF or Mach-O images
|
||||
// you need to subtact out the size of the PE/COFF header to get
|
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// get the offset that matches the link map.
|
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//
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DEBUG ((EFI_D_ERROR, "loadded at 0x%08x (PE/COFF offset) 0x%08x (ELF or Mach-O offset) 0x%08x\n", ImageBase, Offset, Offset - PeCoffSizeOfHeader));
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}
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DEBUG_CODE_END ();
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DEBUG ((EFI_D_ERROR, " R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));
|
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DEBUG ((EFI_D_ERROR, " R4 0x%08x R5 0x%08x R6 0x%08x R7 0x%08x\n", SystemContext.SystemContextArm->R4, SystemContext.SystemContextArm->R5, SystemContext.SystemContextArm->R6, SystemContext.SystemContextArm->R7));
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DEBUG ((EFI_D_ERROR, " R8 0x%08x R9 0x%08x R10 0x%08x R11 0x%08x\n", SystemContext.SystemContextArm->R8, SystemContext.SystemContextArm->R9, SystemContext.SystemContextArm->R10, SystemContext.SystemContextArm->R11));
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||||
DEBUG ((EFI_D_ERROR, "R12 0x%08x SP 0x%08x LR 0x%08x PC 0x%08x\n", SystemContext.SystemContextArm->R12, SystemContext.SystemContextArm->SP, SystemContext.SystemContextArm->LR, SystemContext.SystemContextArm->PC));
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DEBUG ((EFI_D_ERROR, "DFSR 0x%08x DFAR 0x%08x IFSR 0x%08x IFAR 0x%08x\n\n", SystemContext.SystemContextArm->DFSR, SystemContext.SystemContextArm->DFAR, SystemContext.SystemContextArm->IFSR, SystemContext.SystemContextArm->IFAR));
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||||
|
||||
ASSERT (FALSE);
|
||||
// while (TRUE) {
|
||||
// CpuSleep ();
|
||||
// }
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -195,6 +296,11 @@ InitializeExceptions (
|
|||
BOOLEAN Enabled;
|
||||
EFI_PHYSICAL_ADDRESS Base;
|
||||
|
||||
Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&gDebugImageTableHeader);
|
||||
if (EFI_ERROR (Status)) {
|
||||
gDebugImageTableHeader = NULL;
|
||||
}
|
||||
|
||||
//
|
||||
// Disable interrupts
|
||||
//
|
||||
|
|
|
|||
|
|
@ -16,6 +16,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|||
|
||||
#include "CpuDxe.h"
|
||||
|
||||
//
|
||||
// For debug switch me back to to EFI_D_PAGE when done
|
||||
//
|
||||
#define L_EFI_D_PAGE EFI_D_ERROR
|
||||
|
||||
//
|
||||
// Translation/page table definitions
|
||||
//
|
||||
|
|
@ -170,13 +175,12 @@ SectionToGcdAttributes (
|
|||
break;
|
||||
default:
|
||||
return EFI_UNSUPPORTED;
|
||||
break;
|
||||
}
|
||||
|
||||
// determine protection attributes
|
||||
switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {
|
||||
case ARM_SECTION_NO_ACCESS: // no read, no write
|
||||
*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
|
||||
//*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;
|
||||
break;
|
||||
|
||||
case ARM_SECTION_PRIV_ACCESS_ONLY:
|
||||
|
|
@ -193,7 +197,6 @@ SectionToGcdAttributes (
|
|||
|
||||
default:
|
||||
return EFI_UNSUPPORTED;
|
||||
break;
|
||||
}
|
||||
|
||||
// now process eXectue Never attribute
|
||||
|
|
@ -204,6 +207,132 @@ SectionToGcdAttributes (
|
|||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Searches memory descriptors covered by given memory range.
|
||||
|
||||
This function searches into the Gcd Memory Space for descriptors
|
||||
(from StartIndex to EndIndex) that contains the memory range
|
||||
specified by BaseAddress and Length.
|
||||
|
||||
@param MemorySpaceMap Gcd Memory Space Map as array.
|
||||
@param NumberOfDescriptors Number of descriptors in map.
|
||||
@param BaseAddress BaseAddress for the requested range.
|
||||
@param Length Length for the requested range.
|
||||
@param StartIndex Start index into the Gcd Memory Space Map.
|
||||
@param EndIndex End index into the Gcd Memory Space Map.
|
||||
|
||||
@retval EFI_SUCCESS Search successfully.
|
||||
@retval EFI_NOT_FOUND The requested descriptors does not exist.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
SearchGcdMemorySpaces (
|
||||
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
|
||||
IN UINTN NumberOfDescriptors,
|
||||
IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
||||
IN UINT64 Length,
|
||||
OUT UINTN *StartIndex,
|
||||
OUT UINTN *EndIndex
|
||||
)
|
||||
{
|
||||
UINTN Index;
|
||||
|
||||
*StartIndex = 0;
|
||||
*EndIndex = 0;
|
||||
for (Index = 0; Index < NumberOfDescriptors; Index++) {
|
||||
if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
|
||||
BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
|
||||
*StartIndex = Index;
|
||||
}
|
||||
if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
|
||||
BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
|
||||
*EndIndex = Index;
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
}
|
||||
return EFI_NOT_FOUND;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Sets the attributes for a specified range in Gcd Memory Space Map.
|
||||
|
||||
This function sets the attributes for a specified range in
|
||||
Gcd Memory Space Map.
|
||||
|
||||
@param MemorySpaceMap Gcd Memory Space Map as array
|
||||
@param NumberOfDescriptors Number of descriptors in map
|
||||
@param BaseAddress BaseAddress for the range
|
||||
@param Length Length for the range
|
||||
@param Attributes Attributes to set
|
||||
|
||||
@retval EFI_SUCCESS Memory attributes set successfully
|
||||
@retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
SetGcdMemorySpaceAttributes (
|
||||
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
|
||||
IN UINTN NumberOfDescriptors,
|
||||
IN EFI_PHYSICAL_ADDRESS BaseAddress,
|
||||
IN UINT64 Length,
|
||||
IN UINT64 Attributes
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINTN Index;
|
||||
UINTN StartIndex;
|
||||
UINTN EndIndex;
|
||||
EFI_PHYSICAL_ADDRESS RegionStart;
|
||||
UINT64 RegionLength;
|
||||
|
||||
//
|
||||
// Get all memory descriptors covered by the memory range
|
||||
//
|
||||
Status = SearchGcdMemorySpaces (
|
||||
MemorySpaceMap,
|
||||
NumberOfDescriptors,
|
||||
BaseAddress,
|
||||
Length,
|
||||
&StartIndex,
|
||||
&EndIndex
|
||||
);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Go through all related descriptors and set attributes accordingly
|
||||
//
|
||||
for (Index = StartIndex; Index <= EndIndex; Index++) {
|
||||
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
|
||||
continue;
|
||||
}
|
||||
//
|
||||
// Calculate the start and end address of the overlapping range
|
||||
//
|
||||
if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {
|
||||
RegionStart = BaseAddress;
|
||||
} else {
|
||||
RegionStart = MemorySpaceMap[Index].BaseAddress;
|
||||
}
|
||||
if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
|
||||
RegionLength = BaseAddress + Length - RegionStart;
|
||||
} else {
|
||||
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
|
||||
}
|
||||
//
|
||||
// Set memory attributes according to MTRR attribute and the original attribute of descriptor
|
||||
//
|
||||
gDS->SetMemorySpaceAttributes (
|
||||
RegionStart,
|
||||
RegionLength,
|
||||
(MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)
|
||||
);
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
|
|
@ -211,20 +340,31 @@ SyncCacheConfig (
|
|||
IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT32 i;
|
||||
UINT32 Descriptor;
|
||||
UINT32 SectionAttributes;
|
||||
EFI_PHYSICAL_ADDRESS NextRegionBase;
|
||||
UINT64 NextRegionLength;
|
||||
UINT64 GcdAttributes;
|
||||
UINT32 NextRegionAttributes = 0;
|
||||
EFI_STATUS Status;
|
||||
UINT32 i;
|
||||
UINT32 Descriptor;
|
||||
UINT32 SectionAttributes;
|
||||
EFI_PHYSICAL_ADDRESS NextRegionBase;
|
||||
UINT64 NextRegionLength;
|
||||
UINT64 GcdAttributes;
|
||||
UINT32 NextRegionAttributes = 0;
|
||||
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
|
||||
UINTN NumberOfDescriptors;
|
||||
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
|
||||
|
||||
|
||||
DEBUG ((L_EFI_D_PAGE, "SyncCacheConfig()\n"));
|
||||
|
||||
// This code assumes MMU is enabled and filed with section translations
|
||||
ASSERT (ArmMmuEnabled ());
|
||||
|
||||
//
|
||||
// Get the memory space map from GCD
|
||||
//
|
||||
MemorySpaceMap = NULL;
|
||||
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
|
||||
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
|
||||
// to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
|
||||
|
|
@ -240,8 +380,8 @@ SyncCacheConfig (
|
|||
NextRegionBase = NextRegionLength = 0;
|
||||
for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {
|
||||
|
||||
// obtain existing descriptor
|
||||
Descriptor = FirstLevelTable[i];
|
||||
// obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section
|
||||
Descriptor = FirstLevelTable[i] | (ARM_SECTION_BASE_MASK & (i << ARM_SECTION_BASE_SHIFT));
|
||||
|
||||
// extract attributes (cacheability and permissions)
|
||||
SectionAttributes = Descriptor & 0xDEC;
|
||||
|
|
@ -254,11 +394,11 @@ SyncCacheConfig (
|
|||
|
||||
// convert section entry attributes to GCD bitmask
|
||||
Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
// update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
|
||||
Status = gDS->SetMemorySpaceAttributes (NextRegionBase, NextRegionLength, GcdAttributes);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
|
||||
|
||||
|
||||
// start on a new region
|
||||
NextRegionLength = 0;
|
||||
|
|
@ -343,12 +483,11 @@ UpdatePageEntries (
|
|||
// Cause a page fault if these ranges are accessed.
|
||||
EntryMask = 0x3;
|
||||
EntryValue = 0;
|
||||
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
|
||||
DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
|
||||
break;
|
||||
|
||||
default:
|
||||
return EFI_UNSUPPORTED;
|
||||
break;
|
||||
}
|
||||
|
||||
// obtain page table base
|
||||
|
|
@ -369,7 +508,7 @@ UpdatePageEntries (
|
|||
Descriptor = FirstLevelTable[FirstLevelIdx];
|
||||
|
||||
// does this descriptor need to be converted from section entry to 4K pages?
|
||||
if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_SECTION ) {
|
||||
if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {
|
||||
Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);
|
||||
if (EFI_ERROR(Status)) {
|
||||
// exit for loop
|
||||
|
|
@ -385,7 +524,7 @@ UpdatePageEntries (
|
|||
|
||||
// calculate index into the page table
|
||||
PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;
|
||||
ASSERT(PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);
|
||||
ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);
|
||||
|
||||
// get the entry
|
||||
PageTableEntry = PageTable[PageTableIndex];
|
||||
|
|
@ -436,35 +575,39 @@ UpdateSectionEntries (
|
|||
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
|
||||
// EntryValue: values at bit positions specified by EntryMask
|
||||
|
||||
// Make sure we handle a section range that is unmapped
|
||||
EntryMask = ARM_DESC_TYPE_MASK;
|
||||
EntryValue = ARM_DESC_TYPE_SECTION;
|
||||
|
||||
// Although the PI spec is unclear on this the GCD guarantees that only
|
||||
// one Attribute bit is set at a time, so we can safely use a switch statement
|
||||
switch(Attributes) {
|
||||
case EFI_MEMORY_UC:
|
||||
// modify cacheability attributes
|
||||
EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
// map to strongly ordered
|
||||
EntryValue = 0; // TEX[2:0] = 0, C=0, B=0
|
||||
EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0
|
||||
break;
|
||||
|
||||
case EFI_MEMORY_WC:
|
||||
// modify cacheability attributes
|
||||
EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
// map to normal non-cachable
|
||||
EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
|
||||
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
|
||||
break;
|
||||
|
||||
case EFI_MEMORY_WT:
|
||||
// modify cacheability attributes
|
||||
EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
// write through with no-allocate
|
||||
EntryValue = ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0
|
||||
EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0
|
||||
break;
|
||||
|
||||
case EFI_MEMORY_WB:
|
||||
// modify cacheability attributes
|
||||
EntryMask = ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
EntryMask |= ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B;
|
||||
// write back (with allocate)
|
||||
EntryValue = (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1
|
||||
EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1
|
||||
break;
|
||||
|
||||
case EFI_MEMORY_WP:
|
||||
|
|
@ -473,15 +616,13 @@ UpdateSectionEntries (
|
|||
case EFI_MEMORY_UCE:
|
||||
// cannot be implemented UEFI definition unclear for ARM
|
||||
// Cause a page fault if these ranges are accessed.
|
||||
EntryMask = 0x3;
|
||||
EntryValue = 0;
|
||||
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
|
||||
EntryValue = ARM_DESC_TYPE_FAULT;
|
||||
DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
return EFI_UNSUPPORTED;
|
||||
break;
|
||||
}
|
||||
|
||||
// obtain page table base
|
||||
|
|
@ -499,7 +640,7 @@ UpdateSectionEntries (
|
|||
Descriptor = FirstLevelTable[FirstLevelIdx + i];
|
||||
|
||||
// has this descriptor already been coverted to pages?
|
||||
if ((Descriptor & ARM_DESC_TYPE_MASK) == ARM_DESC_TYPE_PAGE_TABLE ) {
|
||||
if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {
|
||||
// forward this 1MB range to page table function instead
|
||||
Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);
|
||||
} else {
|
||||
|
|
@ -539,14 +680,14 @@ ConvertSectionToPages (
|
|||
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
|
||||
volatile ARM_PAGE_TABLE_ENTRY *PageTable;
|
||||
|
||||
DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
|
||||
DEBUG ((L_EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
|
||||
|
||||
// obtain page table base
|
||||
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();
|
||||
|
||||
// calculate index into first level translation table for start of modification
|
||||
FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;
|
||||
ASSERT(FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
|
||||
ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);
|
||||
|
||||
// get section attributes and convert to page attributes
|
||||
SectionDescriptor = FirstLevelTable[FirstLevelIdx];
|
||||
|
|
@ -588,7 +729,9 @@ ConvertSectionToPages (
|
|||
// flush d-cache so descriptors make it back to uncached memory for subsequent table walks
|
||||
// TODO: change to use only PageTable base and length
|
||||
// ArmInvalidateDataCache ();
|
||||
InvalidateDataCacheRange ((VOID *)&PageTableAddr, EFI_PAGE_SIZE);
|
||||
DEBUG ((EFI_D_ERROR, "InvalidateDataCacheRange (%x, %x)\n", (UINTN)PageTableAddr, EFI_PAGE_SIZE));
|
||||
|
||||
InvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, EFI_PAGE_SIZE);
|
||||
|
||||
// formulate page table entry, Domain=0, NS=0
|
||||
PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;
|
||||
|
|
@ -613,11 +756,11 @@ SetMemoryAttributes (
|
|||
|
||||
if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {
|
||||
// is the base and length a multiple of 1 MB?
|
||||
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
|
||||
DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
|
||||
Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);
|
||||
} else {
|
||||
// base and/or length is not a multiple of 1 MB
|
||||
DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
|
||||
DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));
|
||||
Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);
|
||||
}
|
||||
|
||||
|
|
@ -664,8 +807,10 @@ CpuSetMemoryAttributes (
|
|||
IN UINT64 Attributes
|
||||
)
|
||||
{
|
||||
DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));
|
||||
if ( ((BaseAddress & (EFI_PAGE_SIZE-1)) != 0) || ((Length & (EFI_PAGE_SIZE-1)) != 0)){
|
||||
// minimum granularity is EFI_PAGE_SIZE (4KB on ARM)
|
||||
DEBUG ((L_EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is EFI_PAGE_SIZE\n", BaseAddress, Length, Attributes));
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
|
|
@ -698,13 +843,13 @@ CpuConvertPagesToUncachedVirtualAddress (
|
|||
*Attributes = GcdDescriptor.Attributes;
|
||||
}
|
||||
}
|
||||
|
||||
ASSERT (FALSE);
|
||||
//
|
||||
// Make this address range page fault if accessed. If it is a DMA buffer than this would
|
||||
// be the PCI address. Code should always use the CPU address, and we will or in VirtualMask
|
||||
// to that address.
|
||||
//
|
||||
Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_XP, 0);
|
||||
Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);
|
||||
if (!EFI_ERROR (Status)) {
|
||||
Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);
|
||||
}
|
||||
|
|
@ -715,7 +860,7 @@ CpuConvertPagesToUncachedVirtualAddress (
|
|||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
CpuFreeConvertedPages (
|
||||
CpuReconvertPagesPages (
|
||||
IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,
|
||||
IN EFI_PHYSICAL_ADDRESS Address,
|
||||
IN UINTN Length,
|
||||
|
|
@ -728,7 +873,7 @@ CpuFreeConvertedPages (
|
|||
//
|
||||
// Unmap the alaised Address
|
||||
//
|
||||
Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_XP, 0);
|
||||
Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);
|
||||
if (!EFI_ERROR (Status)) {
|
||||
//
|
||||
// Restore atttributes
|
||||
|
|
@ -742,7 +887,7 @@ CpuFreeConvertedPages (
|
|||
|
||||
VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {
|
||||
CpuConvertPagesToUncachedVirtualAddress,
|
||||
CpuFreeConvertedPages
|
||||
CpuReconvertPagesPages
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -263,6 +263,7 @@ ArmSetTranslationTableBaseAddress (
|
|||
VOID *
|
||||
EFIAPI
|
||||
ArmGetTranslationTableBaseAddress (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ EFI_STATUS
|
|||
|
||||
struct _VIRTUAL_UNCACHED_PAGES_PROTOCOL {
|
||||
CONVERT_PAGES_TO_UNCACHED_VIRTUAL_ADDRESS ConvertPages;
|
||||
FREE_CONVERTED_PAGES FreeConvertedPages;
|
||||
FREE_CONVERTED_PAGES RevertPages;
|
||||
};
|
||||
|
||||
extern EFI_GUID gVirtualUncachedPagesProtocolGuid;
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -27,19 +27,15 @@ CacheRangeOperation (
|
|||
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
|
||||
UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
|
||||
|
||||
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold))
|
||||
{
|
||||
CacheOperation();
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
|
||||
CacheOperation ();
|
||||
} else {
|
||||
// Align address (rounding down)
|
||||
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
|
||||
UINTN EndAddress = (UINTN)Start + Length;
|
||||
|
||||
// Perform the line operation on an address in each cache line
|
||||
while (AlignedAddress < EndAddress)
|
||||
{
|
||||
while (AlignedAddress < EndAddress) {
|
||||
LineOperation(AlignedAddress);
|
||||
AlignedAddress += ArmCacheLineLength;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ ArmSetTranslationTableBaseAddress
|
|||
mcr p15,0,r0,c2,c0,0
|
||||
bx lr
|
||||
|
||||
ArmSetTranslationTableBaseAddress
|
||||
ArmGetTranslationTableBaseAddress
|
||||
mrc p15,0,r0,c2,c0,0
|
||||
bx lr
|
||||
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ UncachedInternalAllocateAlignedPages (
|
|||
|
||||
|
||||
|
||||
EFI_CPU_ARCH_PROTOCOL *gCpu;
|
||||
EFI_CPU_ARCH_PROTOCOL *gDebugUncachedCpu;
|
||||
VIRTUAL_UNCACHED_PAGES_PROTOCOL *gVirtualUncachedPages;
|
||||
|
||||
//
|
||||
|
|
@ -641,7 +641,7 @@ DebugUncachedMemoryAllocationLibConstructor (
|
|||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
|
||||
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gDebugUncachedCpu);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
Status = gBS->LocateProtocol (&gVirtualUncachedPagesProtocolGuid, NULL, (VOID **)&gVirtualUncachedPages);
|
||||
|
|
|
|||
|
|
@ -29,19 +29,19 @@
|
|||
MdePkg/MdePkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
UefiMemoryAllocationLib
|
||||
MemoryAllocationLib
|
||||
ArmLib
|
||||
|
||||
[Protocols]
|
||||
gEfiCpuArchProtocolGuid
|
||||
gVirtualUncachedPagesProtocolGuid
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask
|
||||
|
||||
|
||||
[Depex]
|
||||
gEfiCpuArchProtocolGuid
|
||||
gVirtualUncachedPagesProtocolGuid
|
||||
gEfiCpuArchProtocolGuid AND gVirtualUncachedPagesProtocolGuid
|
||||
|
|
@ -40,6 +40,7 @@
|
|||
|
||||
|
||||
ArmLib|ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
|
||||
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
|
||||
|
||||
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
|
||||
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
|
||||
|
|
@ -90,7 +91,10 @@
|
|||
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
|
||||
EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
|
||||
|
||||
UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
|
||||
# UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
|
||||
UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
|
||||
|
||||
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
|
||||
|
||||
TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
|
||||
OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
|
||||
|
|
@ -206,49 +210,29 @@
|
|||
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
|
||||
|
||||
# DEBUG_ASSERT_ENABLED 0x01
|
||||
|
||||
# DEBUG_PRINT_ENABLED 0x02
|
||||
|
||||
# DEBUG_CODE_ENABLED 0x04
|
||||
|
||||
# CLEAR_MEMORY_ENABLED 0x08
|
||||
|
||||
# ASSERT_BREAKPOINT_ENABLED 0x10
|
||||
|
||||
# ASSERT_DEADLOOP_ENABLED 0x20
|
||||
|
||||
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
|
||||
|
||||
# DEBUG_INIT 0x00000001 // Initialization
|
||||
|
||||
# DEBUG_WARN 0x00000002 // Warnings
|
||||
|
||||
# DEBUG_LOAD 0x00000004 // Load events
|
||||
|
||||
# DEBUG_FS 0x00000008 // EFI File system
|
||||
|
||||
# DEBUG_POOL 0x00000010 // Alloc & Free's
|
||||
|
||||
# DEBUG_PAGE 0x00000020 // Alloc & Free's
|
||||
|
||||
# DEBUG_INFO 0x00000040 // Verbose
|
||||
|
||||
# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
|
||||
|
||||
# DEBUG_VARIABLE 0x00000100 // Variable
|
||||
|
||||
# DEBUG_BM 0x00000400 // Boot Manager
|
||||
|
||||
# DEBUG_BLKIO 0x00001000 // BlkIo Driver
|
||||
|
||||
# DEBUG_NET 0x00004000 // SNI Driver
|
||||
|
||||
# DEBUG_UNDI 0x00010000 // UNDI Driver
|
||||
|
||||
# DEBUG_LOADFILE 0x00020000 // UNDI Driver
|
||||
|
||||
# DEBUG_EVENT 0x00080000 // Event messages
|
||||
|
||||
# DEBUG_ERROR 0x80000000 // Error
|
||||
|
||||
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004
|
||||
|
|
|
|||
|
|
@ -58,29 +58,23 @@ InitCache (
|
|||
MemoryTable[0].Length = MemoryLength;
|
||||
MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
|
||||
|
||||
// Uncached DDR Mirror
|
||||
MemoryTable[1].PhysicalBase = MemoryBase;
|
||||
MemoryTable[1].VirtualBase = MemoryBase | UncachedMemoryMask;
|
||||
MemoryTable[1].Length = MemoryLength;
|
||||
MemoryTable[1].Attributes = DDR_ATTRIBUTES_UNCACHED;
|
||||
|
||||
// SOC Registers. L3 interconnects
|
||||
MemoryTable[2].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
|
||||
MemoryTable[2].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
|
||||
MemoryTable[2].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
|
||||
MemoryTable[2].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;
|
||||
MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
|
||||
MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
|
||||
MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
|
||||
MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;
|
||||
|
||||
// SOC Registers. L4 interconnects
|
||||
MemoryTable[3].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
|
||||
MemoryTable[3].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
|
||||
MemoryTable[3].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
|
||||
MemoryTable[3].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;
|
||||
MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
|
||||
MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
|
||||
MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
|
||||
MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;
|
||||
|
||||
// End of Table
|
||||
MemoryTable[4].PhysicalBase = 0;
|
||||
MemoryTable[4].VirtualBase = 0;
|
||||
MemoryTable[4].Length = 0;
|
||||
MemoryTable[4].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
||||
MemoryTable[3].PhysicalBase = 0;
|
||||
MemoryTable[3].VirtualBase = 0;
|
||||
MemoryTable[3].Length = 0;
|
||||
MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
|
||||
|
||||
ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue