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Coreboot*Pkg: Retire CorebootPayloadPkg and CorebootModulePkg 

RFC: https://edk2.groups.io/g/devel/message/39126

Since UefiPayloadPkg in EDK2 supports Coreboot and Slim Bootloader,
and I don't receive any concerns for the RFC to remove CorebootModulePkg
and CorebootPayloadPkg from EDK2, here is the action patch to remove
CorebootPayloadPkg and CorebootModulePkg.

Signed-off-by: Guo Dong <guo.dong@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
This commit is contained in:
Maurice Ma 2019-05-10 10:39:08 -07:00
parent ae3c247dbc
commit f684c3f5ee
58 changed files with 0 additions and 12812 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

158
CorebootModulePkg/CbSupportDxe/CbSupportDxe.c
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@ -1,158 +0,0 @@
/** @file
This driver will report some MMIO/IO resources to dxe core, extract smbios and acpi
tables from coreboot and install.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "CbSupportDxe.h"
/**
Reserve MMIO/IO resource in GCD
@param IsMMIO Flag of whether it is mmio resource or io resource.
@param GcdType Type of the space.
@param BaseAddress Base address of the space.
@param Length Length of the space.
@param Alignment Align with 2^Alignment
@param ImageHandle Handle for the image of this driver.
@retval EFI_SUCCESS Reserve successful
**/
EFI_STATUS
CbReserveResourceInGcd (
IN BOOLEAN IsMMIO,
IN UINTN GcdType,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINTN Alignment,
IN EFI_HANDLE ImageHandle
)
{
EFI_STATUS Status;
if (IsMMIO) {
Status = gDS->AddMemorySpace (
GcdType,
BaseAddress,
Length,
EFI_MEMORY_UC
);
if (EFI_ERROR (Status)) {
DEBUG ((
EFI_D_ERROR,
"Failed to add memory space :0x%lx 0x%lx\n",
BaseAddress,
Length
));
}
ASSERT_EFI_ERROR (Status);
Status = gDS->AllocateMemorySpace (
EfiGcdAllocateAddress,
GcdType,
Alignment,
Length,
&BaseAddress,
ImageHandle,
NULL
);
ASSERT_EFI_ERROR (Status);
} else {
Status = gDS->AddIoSpace (
GcdType,
BaseAddress,
Length
);
ASSERT_EFI_ERROR (Status);
Status = gDS->AllocateIoSpace (
EfiGcdAllocateAddress,
GcdType,
Alignment,
Length,
&BaseAddress,
ImageHandle,
NULL
);
ASSERT_EFI_ERROR (Status);
}
return Status;
}
/**
Main entry for the Coreboot Support DXE module.
@param[in] ImageHandle The firmware allocated handle for the EFI image.
@param[in] SystemTable A pointer to the EFI System Table.
@retval EFI_SUCCESS The entry point is executed successfully.
@retval other Some error occurs when executing this entry point.
**/
EFI_STATUS
EFIAPI
CbDxeEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
EFI_HOB_GUID_TYPE *GuidHob;
SYSTEM_TABLE_INFO *pSystemTableInfo;
FRAME_BUFFER_INFO *FbInfo;
Status = EFI_SUCCESS;
//
// Report MMIO/IO Resources
//
Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFEC00000, SIZE_4KB, 0, SystemTable); // IOAPIC
ASSERT_EFI_ERROR (Status);
Status = CbReserveResourceInGcd (TRUE, EfiGcdMemoryTypeMemoryMappedIo, 0xFED00000, SIZE_1KB, 0, SystemTable); // HPET
ASSERT_EFI_ERROR (Status);
//
// Find the system table information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiSystemTableInfoGuid);
ASSERT (GuidHob != NULL);
pSystemTableInfo = (SYSTEM_TABLE_INFO *)GET_GUID_HOB_DATA (GuidHob);
//
// Install Acpi Table
//
if (pSystemTableInfo->AcpiTableBase != 0 && pSystemTableInfo->AcpiTableSize != 0) {
DEBUG ((EFI_D_ERROR, "Install Acpi Table at 0x%lx, length 0x%x\n", pSystemTableInfo->AcpiTableBase, pSystemTableInfo->AcpiTableSize));
Status = gBS->InstallConfigurationTable (&gEfiAcpiTableGuid, (VOID *)(UINTN)pSystemTableInfo->AcpiTableBase);
ASSERT_EFI_ERROR (Status);
}
//
// Install Smbios Table
//
if (pSystemTableInfo->SmbiosTableBase != 0 && pSystemTableInfo->SmbiosTableSize != 0) {
DEBUG ((EFI_D_ERROR, "Install Smbios Table at 0x%lx, length 0x%x\n", pSystemTableInfo->SmbiosTableBase, pSystemTableInfo->SmbiosTableSize));
Status = gBS->InstallConfigurationTable (&gEfiSmbiosTableGuid, (VOID *)(UINTN)pSystemTableInfo->SmbiosTableBase);
ASSERT_EFI_ERROR (Status);
}
//
// Find the frame buffer information and update PCDs
//
GuidHob = GetFirstGuidHob (&gUefiFrameBufferInfoGuid);
if (GuidHob != NULL) {
FbInfo = (FRAME_BUFFER_INFO *)GET_GUID_HOB_DATA (GuidHob);
Status = PcdSet32S (PcdVideoHorizontalResolution, FbInfo->HorizontalResolution);
ASSERT_EFI_ERROR (Status);
Status = PcdSet32S (PcdVideoVerticalResolution, FbInfo->VerticalResolution);
ASSERT_EFI_ERROR (Status);
Status = PcdSet32S (PcdSetupVideoHorizontalResolution, FbInfo->HorizontalResolution);
ASSERT_EFI_ERROR (Status);
Status = PcdSet32S (PcdSetupVideoVerticalResolution, FbInfo->VerticalResolution);
ASSERT_EFI_ERROR (Status);
}
return EFI_SUCCESS;
}

30
CorebootModulePkg/CbSupportDxe/CbSupportDxe.h
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@ -1,30 +0,0 @@
/** @file
The header file of Coreboot Support DXE.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __DXE_COREBOOT_SUPPORT_H__
#define __DXE_COREBOOT_SUPPORT_H__
#include <PiDxe.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Guid/Acpi.h>
#include <Guid/SmBios.h>
#include <Guid/SystemTableInfoGuid.h>
#include <Guid/AcpiBoardInfoGuid.h>
#include <Guid/FrameBufferInfoGuid.h>
#include <IndustryStandard/Acpi.h>
#endif

60
CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
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@ -1,60 +0,0 @@
## @file
# Coreboot Support DXE Module
#
# Report some MMIO/IO resources to dxe core, extract smbios and acpi tables from coreboot and install.
#
# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CbSupportDxe
FILE_GUID = C68DAA4E-7AB5-41e8-A91D-5954421053F3
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = CbDxeEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
CbSupportDxe.c
CbSupportDxe.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
CorebootModulePkg/CorebootModulePkg.dec
[LibraryClasses]
UefiDriverEntryPoint
UefiBootServicesTableLib
DxeServicesTableLib
DebugLib
BaseMemoryLib
UefiLib
HobLib
[Guids]
gEfiAcpiTableGuid
gEfiSmbiosTableGuid
gUefiSystemTableInfoGuid
gUefiAcpiBoardInfoGuid
gUefiFrameBufferInfoGuid
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution
[Depex]
TRUE

440
CorebootModulePkg/CbSupportPei/CbSupportPei.c
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@ -1,440 +0,0 @@
/** @file
This PEIM will parse coreboot table in memory and report resource information into pei core.
This file contains the main entrypoint of the PEIM.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "CbSupportPei.h"
#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
{ EfiACPIReclaimMemory, FixedPcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory) },
{ EfiACPIMemoryNVS, FixedPcdGet32 (PcdMemoryTypeEfiACPIMemoryNVS) },
{ EfiReservedMemoryType, FixedPcdGet32 (PcdMemoryTypeEfiReservedMemoryType) },
{ EfiRuntimeServicesData, FixedPcdGet32 (PcdMemoryTypeEfiRuntimeServicesData) },
{ EfiRuntimeServicesCode, FixedPcdGet32 (PcdMemoryTypeEfiRuntimeServicesCode) },
{ EfiMaxMemoryType, 0 }
};
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEfiPeiMasterBootModePpiGuid,
NULL
}
};
/**
Create memory mapped io resource hob.
@param MmioBase Base address of the memory mapped io range
@param MmioSize Length of the memory mapped io range
**/
VOID
BuildMemoryMappedIoRangeHob (
EFI_PHYSICAL_ADDRESS MmioBase,
UINT64 MmioSize
)
{
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_MAPPED_IO,
(EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED),
MmioBase,
MmioSize
);
BuildMemoryAllocationHob (
MmioBase,
MmioSize,
EfiMemoryMappedIO
);
}
/**
Check the integrity of firmware volume header
@param[in] FwVolHeader A pointer to a firmware volume header
@retval TRUE The firmware volume is consistent
@retval FALSE The firmware volume has corrupted.
**/
STATIC
BOOLEAN
IsFvHeaderValid (
IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
)
{
UINT16 Checksum;
// Skip nv storage fv
if (CompareMem (&FwVolHeader->FileSystemGuid, &gEfiFirmwareFileSystem2Guid, sizeof(EFI_GUID)) != 0 ) {
return FALSE;
}
if ( (FwVolHeader->Revision != EFI_FVH_REVISION) ||
(FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
(FwVolHeader->FvLength == ((UINTN) -1)) ||
((FwVolHeader->HeaderLength & 0x01 ) !=0) ) {
return FALSE;
}
Checksum = CalculateCheckSum16 ((UINT16 *) FwVolHeader, FwVolHeader->HeaderLength);
if (Checksum != 0) {
DEBUG (( DEBUG_ERROR,
"ERROR - Invalid Firmware Volume Header Checksum, change 0x%04x to 0x%04x\r\n",
FwVolHeader->Checksum,
(UINT16)( Checksum + FwVolHeader->Checksum )));
return FALSE;
}
return TRUE;
}
/**
Install FvInfo PPI and create fv hobs for remained fvs
**/
VOID
CbPeiReportRemainedFvs (
VOID
)
{
UINT8* TempPtr;
UINT8* EndPtr;
TempPtr = (UINT8* )(UINTN) PcdGet32 (PcdPayloadFdMemBase);
EndPtr = (UINT8* )(UINTN) (PcdGet32 (PcdPayloadFdMemBase) + PcdGet32 (PcdPayloadFdMemSize));
for (;TempPtr < EndPtr;) {
if (IsFvHeaderValid ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)) {
if (TempPtr != (UINT8* )(UINTN) PcdGet32 (PcdPayloadFdMemBase)) {
// Skip the PEI FV
DEBUG((EFI_D_ERROR, "Found one valid fv : 0x%lx.\n", TempPtr, ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength));
PeiServicesInstallFvInfoPpi (
NULL,
(VOID *) (UINTN) TempPtr,
(UINT32) (UINTN) ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength,
NULL,
NULL
);
BuildFvHob ((EFI_PHYSICAL_ADDRESS)(UINTN) TempPtr, ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength);
}
}
TempPtr += ((EFI_FIRMWARE_VOLUME_HEADER* )TempPtr)->FvLength;
}
}
/**
Based on memory base, size and type, build resource descripter HOB.
@param Base Memory base address.
@param Size Memory size.
@param Type Memory type.
@param Param A pointer to CB_MEM_INFO.
@retval EFI_SUCCESS if it completed successfully.
**/
EFI_STATUS
CbMemInfoCallback (
UINT64 Base,
UINT64 Size,
UINT32 Type,
VOID *Param
)
{
CB_MEM_INFO *MemInfo;
UINTN Attribue;
Attribue = EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_TESTED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE;
if ((Base < 0x100000) && ((Base + Size) > 0x100000)) {
Size -= (0x100000 - Base);
Base = 0x100000;
}
MemInfo = (CB_MEM_INFO *)Param;
if (Base >= 0x100000) {
if (Type == CB_MEM_RAM) {
if (Base < 0x100000000ULL) {
MemInfo->UsableLowMemTop = (UINT32)(Base + Size);
} else {
Attribue &= ~EFI_RESOURCE_ATTRIBUTE_TESTED;
}
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
Attribue,
(EFI_PHYSICAL_ADDRESS)Base,
Size
);
} else if (Type == CB_MEM_TABLE) {
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_RESERVED,
Attribue,
(EFI_PHYSICAL_ADDRESS)Base,
Size
);
MemInfo->SystemLowMemTop = ((UINT32)(Base + Size) + 0x0FFFFFFF) & 0xF0000000;
} else if (Type == CB_MEM_RESERVED) {
if ((MemInfo->SystemLowMemTop == 0) || (Base < MemInfo->SystemLowMemTop)) {
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_RESERVED,
Attribue,
(EFI_PHYSICAL_ADDRESS)Base,
Size
);
}
}
}
return EFI_SUCCESS;
}
/**
This is the entrypoint of PEIM
@param FileHandle Handle of the file being invoked.
@param PeiServices Describes the list of possible PEI Services.
@retval EFI_SUCCESS if it completed successfully.
**/
EFI_STATUS
EFIAPI
CbPeiEntryPoint (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
EFI_STATUS Status;
UINT64 LowMemorySize;
UINT64 PeiMemSize = SIZE_64MB; // 64 MB
EFI_PHYSICAL_ADDRESS PeiMemBase = 0;
UINT32 RegEax;
UINT8 PhysicalAddressBits;
VOID* pCbHeader;
VOID* pAcpiTable;
UINT32 AcpiTableSize;
VOID* pSmbiosTable;
UINT32 SmbiosTableSize;
SYSTEM_TABLE_INFO* pSystemTableInfo;
FRAME_BUFFER_INFO FbInfo;
FRAME_BUFFER_INFO* pFbInfo;
ACPI_BOARD_INFO* pAcpiBoardInfo;
UINTN PmCtrlRegBase, PmTimerRegBase, ResetRegAddress, ResetValue;
UINTN PmEvtBase;
UINTN PmGpeEnBase;
CB_MEM_INFO CbMemInfo;
//
// Report lower 640KB of RAM. Attribute EFI_RESOURCE_ATTRIBUTE_TESTED
// is intentionally omitted to prevent erasing of the coreboot header
// record before it is processed by CbParseMemoryInfo.
//
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
(
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
),
(EFI_PHYSICAL_ADDRESS)(0),
(UINT64)(0xA0000)
);
BuildResourceDescriptorHob (
EFI_RESOURCE_MEMORY_RESERVED,
(
EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_TESTED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
),
(EFI_PHYSICAL_ADDRESS)(0xA0000),
(UINT64)(0x60000)
);
ZeroMem (&CbMemInfo, sizeof(CbMemInfo));
Status = CbParseMemoryInfo (CbMemInfoCallback, (VOID *)&CbMemInfo);
if (EFI_ERROR(Status)) {
return Status;
}
LowMemorySize = CbMemInfo.UsableLowMemTop;
DEBUG ((EFI_D_INFO, "Low memory 0x%lx\n", LowMemorySize));
DEBUG ((EFI_D_INFO, "SystemLowMemTop 0x%x\n", CbMemInfo.SystemLowMemTop));
//
// Should be 64k aligned
//
PeiMemBase = (LowMemorySize - PeiMemSize) & (~(BASE_64KB - 1));
DEBUG((EFI_D_ERROR, "PeiMemBase: 0x%lx.\n", PeiMemBase));
DEBUG((EFI_D_ERROR, "PeiMemSize: 0x%lx.\n", PeiMemSize));
Status = PeiServicesInstallPeiMemory (
PeiMemBase,
PeiMemSize
);
ASSERT_EFI_ERROR (Status);
//
// Set cache on the physical memory
//
MtrrSetMemoryAttribute (BASE_1MB, LowMemorySize - BASE_1MB, CacheWriteBack);
MtrrSetMemoryAttribute (0, 0xA0000, CacheWriteBack);
//
// Create Memory Type Information HOB
//
BuildGuidDataHob (
&gEfiMemoryTypeInformationGuid,
mDefaultMemoryTypeInformation,
sizeof(mDefaultMemoryTypeInformation)
);
//
// Create Fv hob
//
CbPeiReportRemainedFvs ();
BuildMemoryAllocationHob (
PcdGet32 (PcdPayloadFdMemBase),
PcdGet32 (PcdPayloadFdMemSize),
EfiBootServicesData
);
//
// Build CPU memory space and IO space hob
//
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax;
} else {
PhysicalAddressBits = 36;
}
//
// Create a CPU hand-off information
//
BuildCpuHob (PhysicalAddressBits, 16);
//
// Report Local APIC range
//
BuildMemoryMappedIoRangeHob (0xFEC80000, SIZE_512KB);
//
// Boot mode
//
Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);
ASSERT_EFI_ERROR (Status);
Status = PeiServicesInstallPpi (mPpiBootMode);
ASSERT_EFI_ERROR (Status);
//
// Set pcd to save the upper coreboot header in case the dxecore will
// erase 0~4k memory
//
pCbHeader = NULL;
if ((CbParseGetCbHeader (1, &pCbHeader) == RETURN_SUCCESS)
&& ((UINTN)pCbHeader > BASE_4KB)) {
DEBUG((EFI_D_ERROR, "Actual Coreboot header: %p.\n", pCbHeader));
Status = PcdSet32S (PcdCbHeaderPointer, (UINT32)(UINTN)pCbHeader);
ASSERT_EFI_ERROR (Status);
}
//
// Create guid hob for system tables like acpi table and smbios table
//
pAcpiTable = NULL;
AcpiTableSize = 0;
pSmbiosTable = NULL;
SmbiosTableSize = 0;
Status = CbParseAcpiTable (&pAcpiTable, &AcpiTableSize);
if (EFI_ERROR (Status)) {
// ACPI table is oblidgible
DEBUG ((EFI_D_ERROR, "Failed to find the required acpi table\n"));
ASSERT (FALSE);
}
CbParseSmbiosTable (&pSmbiosTable, &SmbiosTableSize);
pSystemTableInfo = NULL;
pSystemTableInfo = BuildGuidHob (&gUefiSystemTableInfoGuid, sizeof (SYSTEM_TABLE_INFO));
ASSERT (pSystemTableInfo != NULL);
pSystemTableInfo->AcpiTableBase = (UINT64) (UINTN)pAcpiTable;
pSystemTableInfo->AcpiTableSize = AcpiTableSize;
pSystemTableInfo->SmbiosTableBase = (UINT64) (UINTN)pSmbiosTable;
pSystemTableInfo->SmbiosTableSize = SmbiosTableSize;
DEBUG ((EFI_D_ERROR, "Detected Acpi Table at 0x%lx, length 0x%x\n", pSystemTableInfo->AcpiTableBase, pSystemTableInfo->AcpiTableSize));
DEBUG ((EFI_D_ERROR, "Detected Smbios Table at 0x%lx, length 0x%x\n", pSystemTableInfo->SmbiosTableBase, pSystemTableInfo->SmbiosTableSize));
DEBUG ((EFI_D_ERROR, "Create system table info guid hob\n"));
//
// Create guid hob for acpi board information
//
Status = CbParseFadtInfo (&PmCtrlRegBase, &PmTimerRegBase, &ResetRegAddress, &ResetValue, &PmEvtBase, &PmGpeEnBase);
ASSERT_EFI_ERROR (Status);
pAcpiBoardInfo = NULL;
pAcpiBoardInfo = BuildGuidHob (&gUefiAcpiBoardInfoGuid, sizeof (ACPI_BOARD_INFO));
ASSERT (pAcpiBoardInfo != NULL);
pAcpiBoardInfo->PmCtrlRegBase = (UINT64)PmCtrlRegBase;
pAcpiBoardInfo->PmTimerRegBase = (UINT64)PmTimerRegBase;
pAcpiBoardInfo->ResetRegAddress = (UINT64)ResetRegAddress;
pAcpiBoardInfo->ResetValue = (UINT8)ResetValue;
pAcpiBoardInfo->PmEvtBase = (UINT64)PmEvtBase;
pAcpiBoardInfo->PmGpeEnBase = (UINT64)PmGpeEnBase;
DEBUG ((EFI_D_ERROR, "Create acpi board info guid hob\n"));
//
// Create guid hob for frame buffer information
//
ZeroMem (&FbInfo, sizeof (FRAME_BUFFER_INFO));
Status = CbParseFbInfo (&FbInfo);
if (!EFI_ERROR (Status)) {
pFbInfo = BuildGuidHob (&gUefiFrameBufferInfoGuid, sizeof (FRAME_BUFFER_INFO));
ASSERT (pSystemTableInfo != NULL);
CopyMem (pFbInfo, &FbInfo, sizeof (FRAME_BUFFER_INFO));
DEBUG ((EFI_D_ERROR, "Create frame buffer info guid hob\n"));
}
//
// Parse platform specific information from coreboot.
//
Status = CbParsePlatformInfo ();
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "Error when parsing platform info, Status = %r\n", Status));
return Status;
}
//
// Mask off all legacy 8259 interrupt sources
//
IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0xFF);
IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0xFF);
return EFI_SUCCESS;
}

42
CorebootModulePkg/CbSupportPei/CbSupportPei.h
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@ -1,42 +0,0 @@
/** @file
The header file of Coreboot Support PEIM.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __PEI_COREBOOT_SUPPORT_H__
#define __PEI_COREBOOT_SUPPORT_H__
#include <PiPei.h>
#include <Library/PeimEntryPoint.h>
#include <Library/PeiServicesLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/CbParseLib.h>
#include <Library/MtrrLib.h>
#include <Library/IoLib.h>
#include <Library/CbPlatformSupportLib.h>
#include <Guid/SmramMemoryReserve.h>
#include <Guid/MemoryTypeInformation.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Guid/FrameBufferInfoGuid.h>
#include <Guid/SystemTableInfoGuid.h>
#include <Guid/AcpiBoardInfoGuid.h>
#include <Ppi/MasterBootMode.h>
#include "Coreboot.h"
typedef struct {
UINT32 UsableLowMemTop;
UINT32 SystemLowMemTop;
} CB_MEM_INFO;
#endif

74
CorebootModulePkg/CbSupportPei/CbSupportPei.inf
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@ -1,74 +0,0 @@
## @file
# Coreboot Support PEI Module
#
# Parses coreboot table in memory and report resource information into pei core. It will install
# the memory as required.
#
# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CbSupportPeim
FILE_GUID = 352C6AF8-315B-4bd6-B04F-31D4ED1EBE57
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = CbPeiEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
CbSupportPei.c
CbSupportPei.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
CorebootModulePkg/CorebootModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
[LibraryClasses]
PeimEntryPoint
PeiServicesLib
BaseLib
BaseMemoryLib
DebugLib
HobLib
PcdLib
CbParseLib
MtrrLib
IoLib
CbPlatformSupportLib
[Guids]
gEfiSmmPeiSmramMemoryReserveGuid
gEfiMemoryTypeInformationGuid
gEfiFirmwareFileSystem2Guid
gUefiSystemTableInfoGuid
gUefiFrameBufferInfoGuid
gUefiAcpiBoardInfoGuid
[Ppis]
gEfiPeiMasterBootModePpiGuid
[Pcd]
gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemBase
gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemSize
gUefiCorebootModulePkgTokenSpaceGuid.PcdCbHeaderPointer
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
[Depex]
TRUE

59
CorebootModulePkg/CorebootModulePkg.dec
View File

@ -1,59 +0,0 @@
## @file
# Coreboot Support Package
#
# Provides drivers and definitions to support coreboot in EDKII bios.
#
# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = CorebootModulePkg
PACKAGE_GUID = DE1750CE-FEE7-4dd1-8E9C-B7B8BAEBCF4F
PACKAGE_VERSION = 0.1
[Includes]
Include
[LibraryClasses]
CbParseLib|Include/Library/CbParseLib.h
[Guids]
#
## Defines the token space for the Coreboot Module Package PCDs.
#
gUefiCorebootModulePkgTokenSpaceGuid = {0xe6ff49a0, 0x15df, 0x48fd, {0x9a, 0xcf, 0xd7, 0xdc, 0x27, 0x1b, 0x39, 0xd5}}
gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf, 0x89, 0xc4, 0x29, 0x4, 0x33}}
gUefiFrameBufferInfoGuid = {0xdc2cd8bd, 0x402c, 0x4dc4, {0x9b, 0xe0, 0xc, 0x43, 0x2b, 0x7, 0xfa, 0x34}}
gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e, 0xf1, 0x10, 0x6, 0xd9, 0xf}}
[Ppis]
[Protocols]
################################################################################
#
# PCD Declarations section - list of all PCDs Declared by this Package
# Only this package should be providing the
# declaration, other packages should not.
#
################################################################################
[PcdsFixedAtBuild, PcdsPatchableInModule]
## Indicates the base address of the payload binary in memory
gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemBase|0|UINT32|0x10000001
## Provides the size of the payload binary in memory
gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemSize|0|UINT32|0x10000002
## Used to help reduce fragmentation in the EFI memory map
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0x08|UINT32|0x10000012
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0x04|UINT32|0x10000013
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0x04|UINT32|0x00000014
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|0xC0|UINT32|0x00000015
gUefiCorebootModulePkgTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|0x80|UINT32|0x00000016
[PcdsDynamicEx]
gUefiCorebootModulePkgTokenSpaceGuid.PcdCbHeaderPointer|0|UINT32|0x10000003

249
CorebootModulePkg/Include/Coreboot.h
View File

@ -1,249 +0,0 @@
/** @file
Coreboot PEI module include file.
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _COREBOOT_PEI_H_INCLUDED_
#define _COREBOOT_PEI_H_INCLUDED_
#if defined(_MSC_VER)
#pragma warning( disable : 4200 )
#endif
#define DYN_CBMEM_ALIGN_SIZE (4096)
#define IMD_ENTRY_MAGIC (~0xC0389481)
#define CBMEM_ENTRY_MAGIC (~0xC0389479)
struct cbmem_entry {
UINT32 magic;
UINT32 start;
UINT32 size;
UINT32 id;
};
struct cbmem_root {
UINT32 max_entries;
UINT32 num_entries;
UINT32 locked;
UINT32 size;
struct cbmem_entry entries[0];
};
struct imd_entry {
UINT32 magic;
UINT32 start_offset;
UINT32 size;
UINT32 id;
};
struct imd_root {
UINT32 max_entries;
UINT32 num_entries;
UINT32 flags;
UINT32 entry_align;
UINT32 max_offset;
struct imd_entry entries[0];
};
struct cbuint64 {
UINT32 lo;
UINT32 hi;
};
#define CB_HEADER_SIGNATURE 0x4F49424C
struct cb_header {
UINT32 signature;
UINT32 header_bytes;
UINT32 header_checksum;
UINT32 table_bytes;
UINT32 table_checksum;
UINT32 table_entries;
};
struct cb_record {
UINT32 tag;
UINT32 size;
};
#define CB_TAG_UNUSED 0x0000
#define CB_TAG_MEMORY 0x0001
struct cb_memory_range {
struct cbuint64 start;
struct cbuint64 size;
UINT32 type;
};
#define CB_MEM_RAM 1
#define CB_MEM_RESERVED 2
#define CB_MEM_ACPI 3
#define CB_MEM_NVS 4
#define CB_MEM_UNUSABLE 5
#define CB_MEM_VENDOR_RSVD 6
#define CB_MEM_TABLE 16
struct cb_memory {
UINT32 tag;
UINT32 size;
struct cb_memory_range map[0];
};
#define CB_TAG_MAINBOARD 0x0003
struct cb_mainboard {
UINT32 tag;
UINT32 size;
UINT8 vendor_idx;
UINT8 part_number_idx;
UINT8 strings[0];
};
#define CB_TAG_VERSION 0x0004
#define CB_TAG_EXTRA_VERSION 0x0005
#define CB_TAG_BUILD 0x0006
#define CB_TAG_COMPILE_TIME 0x0007
#define CB_TAG_COMPILE_BY 0x0008
#define CB_TAG_COMPILE_HOST 0x0009
#define CB_TAG_COMPILE_DOMAIN 0x000a
#define CB_TAG_COMPILER 0x000b
#define CB_TAG_LINKER 0x000c
#define CB_TAG_ASSEMBLER 0x000d
struct cb_string {
UINT32 tag;
UINT32 size;
UINT8 string[0];
};
#define CB_TAG_SERIAL 0x000f
struct cb_serial {
UINT32 tag;
UINT32 size;
#define CB_SERIAL_TYPE_IO_MAPPED 1
#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
UINT32 type;
UINT32 baseaddr;
UINT32 baud;
UINT32 regwidth;
// Crystal or input frequency to the chip containing the UART.
// Provide the board specific details to allow the payload to
// initialize the chip containing the UART and make independent
// decisions as to which dividers to select and their values
// to eventually arrive at the desired console baud-rate.
UINT32 input_hertz;
// UART PCI address: bus, device, function
// 1 << 31 - Valid bit, PCI UART in use
// Bus << 20
// Device << 15
// Function << 12
UINT32 uart_pci_addr;
};
#define CB_TAG_CONSOLE 0x00010
struct cb_console {
UINT32 tag;
UINT32 size;
UINT16 type;
};
#define CB_TAG_CONSOLE_SERIAL8250 0
#define CB_TAG_CONSOLE_VGA 1 // OBSOLETE
#define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE
#define CB_TAG_CONSOLE_LOGBUF 3
#define CB_TAG_CONSOLE_SROM 4 // OBSOLETE
#define CB_TAG_CONSOLE_EHCI 5
#define CB_TAG_FORWARD 0x00011
struct cb_forward {
UINT32 tag;
UINT32 size;
UINT64 forward;
};
#define CB_TAG_FRAMEBUFFER 0x0012
struct cb_framebuffer {
UINT32 tag;
UINT32 size;
UINT64 physical_address;
UINT32 x_resolution;
UINT32 y_resolution;
UINT32 bytes_per_line;
UINT8 bits_per_pixel;
UINT8 red_mask_pos;
UINT8 red_mask_size;
UINT8 green_mask_pos;
UINT8 green_mask_size;
UINT8 blue_mask_pos;
UINT8 blue_mask_size;
UINT8 reserved_mask_pos;
UINT8 reserved_mask_size;
};
#define CB_TAG_VDAT 0x0015
struct cb_vdat {
UINT32 tag;
UINT32 size; /* size of the entire entry */
UINT64 vdat_addr;
UINT32 vdat_size;
};
#define CB_TAG_TIMESTAMPS 0x0016
#define CB_TAG_CBMEM_CONSOLE 0x0017
#define CB_TAG_MRC_CACHE 0x0018
struct cb_cbmem_tab {
UINT32 tag;
UINT32 size;
UINT64 cbmem_tab;
};
/* Helpful macros */
#define MEM_RANGE_COUNT(_rec) \
(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
#define MEM_RANGE_PTR(_rec, _idx) \
(void *)(((UINT8 *) (_rec)) + sizeof(*(_rec)) \
+ (sizeof((_rec)->map[0]) * (_idx)))
#endif // _COREBOOT_PEI_H_INCLUDED_

26
CorebootModulePkg/Include/Guid/AcpiBoardInfoGuid.h
View File

@ -1,26 +0,0 @@
/** @file
This file defines the hob structure for board related information from acpi table
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __ACPI_BOARD_INFO_GUID_H__
#define __ACPI_BOARD_INFO_GUID_H__
///
/// Board information GUID
///
extern EFI_GUID gUefiAcpiBoardInfoGuid;
typedef struct {
UINT64 PmEvtBase;
UINT64 PmGpeEnBase;
UINT64 PmCtrlRegBase;
UINT64 PmTimerRegBase;
UINT64 ResetRegAddress;
UINT8 ResetValue;
} ACPI_BOARD_INFO;
#endif

34
CorebootModulePkg/Include/Guid/FrameBufferInfoGuid.h
View File

@ -1,34 +0,0 @@
/** @file
This file defines the hob structure for frame buffer device.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __FRAME_BUFFER_INFO_GUID_H__
#define __FRAME_BUFFER_INFO_GUID_H__
///
/// Frame Buffer Information GUID
///
extern EFI_GUID gUefiFrameBufferInfoGuid;
typedef struct {
UINT8 Position; // Position of the color
UINT8 Mask; // The number of bits expressed as a mask
} COLOR_PLACEMENT;
typedef struct {
UINT64 LinearFrameBuffer;
UINT32 HorizontalResolution;
UINT32 VerticalResolution;
UINT32 BitsPerPixel;
UINT16 BytesPerScanLine;
COLOR_PLACEMENT Red;
COLOR_PLACEMENT Green;
COLOR_PLACEMENT Blue;
COLOR_PLACEMENT Reserved;
} FRAME_BUFFER_INFO;
#endif

24
CorebootModulePkg/Include/Guid/SystemTableInfoGuid.h
View File

@ -1,24 +0,0 @@
/** @file
This file defines the hob structure for system tables like ACPI, SMBIOS tables.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __SYSTEM_TABLE_INFO_GUID_H__
#define __SYSTEM_TABLE_INFO_GUID_H__
///
/// System Table Information GUID
///
extern EFI_GUID gUefiSystemTableInfoGuid;
typedef struct {
UINT64 AcpiTableBase;
UINT32 AcpiTableSize;
UINT64 SmbiosTableBase;
UINT32 SmbiosTableSize;
} SYSTEM_TABLE_INFO;
#endif

186
CorebootModulePkg/Include/Library/CbParseLib.h
View File

@ -1,186 +0,0 @@
/** @file
This library will parse the coreboot table in memory and extract those required
information.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Guid/FrameBufferInfoGuid.h>
typedef RETURN_STATUS \
(*CB_MEM_INFO_CALLBACK) (UINT64 Base, UINT64 Size, UINT32 Type, VOID *Param);
/**
Find coreboot record with given Tag from the memory Start in 4096
bytes range.
@param Start The start memory to be searched in
@param Tag The tag id to be found
@retval NULL The Tag is not found.
@retval Others The pointer to the record found.
**/
VOID *
EFIAPI
FindCbTag (
IN VOID *Start,
IN UINT32 Tag
);
/**
Acquire the memory information from the coreboot table in memory.
@param MemInfoCallback The callback routine
@param pParam Pointer to the callback routine parameter
@retval RETURN_SUCCESS Successfully find out the memory information.
@retval RETURN_NOT_FOUND Failed to find the memory information.
**/
RETURN_STATUS
EFIAPI
CbParseMemoryInfo (
IN CB_MEM_INFO_CALLBACK MemInfoCallback,
IN VOID *pParam
);
/**
Acquire the coreboot memory table with the given table id
@param TableId Table id to be searched
@param pMemTable Pointer to the base address of the memory table
@param pMemTableSize Pointer to the size of the memory table
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
EFIAPI
CbParseCbMemTable (
IN UINT32 TableId,
IN VOID** pMemTable,
IN UINT32* pMemTableSize
);
/**
Acquire the acpi table from coreboot
@param pMemTable Pointer to the base address of the memory table
@param pMemTableSize Pointer to the size of the memory table
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
EFIAPI
CbParseAcpiTable (
IN VOID** pMemTable,
IN UINT32* pMemTableSize
);
/**
Acquire the smbios table from coreboot
@param pMemTable Pointer to the base address of the memory table
@param pMemTableSize Pointer to the size of the memory table
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
EFIAPI
CbParseSmbiosTable (
IN VOID** pMemTable,
IN UINT32* pMemTableSize
);
/**
Find the required fadt information
@param pPmCtrlReg Pointer to the address of power management control register
@param pPmTimerReg Pointer to the address of power management timer register
@param pResetReg Pointer to the address of system reset register
@param pResetValue Pointer to the value to be written to the system reset register
@param pPmEvtReg Pointer to the address of power management event register
@param pPmGpeEnReg Pointer to the address of power management GPE enable register
@retval RETURN_SUCCESS Successfully find out all the required fadt information.
@retval RETURN_NOT_FOUND Failed to find the fadt table.
**/
RETURN_STATUS
EFIAPI
CbParseFadtInfo (
IN UINTN* pPmCtrlReg,
IN UINTN* pPmTimerReg,
IN UINTN* pResetReg,
IN UINTN* pResetValue,
IN UINTN* pPmEvtReg,
IN UINTN* pPmGpeEnReg
);
/**
Find the serial port information
@param pRegBase Pointer to the base address of serial port registers
@param pRegAccessType Pointer to the access type of serial port registers
@param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate
@param pInputHertz Pointer to the input clock frequency
@param pUartPciAddr Pointer to the UART PCI bus, dev and func address
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
**/
RETURN_STATUS
EFIAPI
CbParseSerialInfo (
OUT UINT32 *pRegBase,
OUT UINT32 *pRegAccessType,
OUT UINT32 *pRegWidth,
OUT UINT32 *pBaudrate,
OUT UINT32 *pInputHertz,
OUT UINT32 *pUartPciAddr
);
/**
Search for the coreboot table header
@param Level Level of the search depth
@param HeaderPtr Pointer to the pointer of coreboot table header
@retval RETURN_SUCCESS Successfully find the coreboot table header .
@retval RETURN_NOT_FOUND Failed to find the coreboot table header .
**/
RETURN_STATUS
EFIAPI
CbParseGetCbHeader (
IN UINTN Level,
IN VOID** HeaderPtr
);
/**
Find the video frame buffer information
@param pFbInfo Pointer to the FRAME_BUFFER_INFO structure
@retval RETURN_SUCCESS Successfully find the video frame buffer information.
@retval RETURN_NOT_FOUND Failed to find the video frame buffer information .
**/
RETURN_STATUS
EFIAPI
CbParseFbInfo (
IN FRAME_BUFFER_INFO* pFbInfo
);

28
CorebootModulePkg/Include/Library/CbPlatformSupportLib.h
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@ -1,28 +0,0 @@
/** @file
Coreboot Platform Support library. Platform can provide an implementation of this
library class to provide hooks that may be required for some type of
platform features.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef __CB_PLATFORM_SUPPORT_LIB__
#define __CB_PLATFORM_SUPPORT_LIB__
/**
Parse platform specific information from coreboot.
@retval RETURN_SUCCESS The platform specific coreboot support succeeded.
@retval RETURN_DEVICE_ERROR The platform specific coreboot support could not be completed.
**/
EFI_STATUS
EFIAPI
CbParsePlatformInfo (
VOID
);
#endif // __CB_PLATFORM_SUPPORT_LIB__

1089
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
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File diff suppressed because it is too large Load Diff

42
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
View File

@ -1,42 +0,0 @@
## @file
# SerialPortLib instance for 16550 UART.
#
# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = BaseSerialPortLib16550
MODULE_UNI_FILE = BaseSerialPortLib16550.uni
FILE_GUID = 9E7C00CF-355A-4d4e-BF60-0428CFF95540
MODULE_TYPE = BASE
VERSION_STRING = 1.1
LIBRARY_CLASS = SerialPortLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
[LibraryClasses]
PcdLib
IoLib
PlatformHookLib
PciLib
[Sources]
BaseSerialPortLib16550.c
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable ## SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## CONSUMES

16
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
View File

@ -1,16 +0,0 @@
// /** @file
// SerialPortLib instance for 16550 UART.
//
// SerialPortLib instance for 16550 UART.
//
// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
// **/
#string STR_MODULE_ABSTRACT #language en-US "SerialPortLib instance for 16550 UART"
#string STR_MODULE_DESCRIPTION #language en-US "SerialPortLib instance for 16550 UART."

721
CorebootModulePkg/Library/CbParseLib/CbParseLib.c
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@ -1,721 +0,0 @@
/** @file
This library will parse the coreboot table in memory and extract those required
information.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi/UefiBaseType.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/CbParseLib.h>
#include <IndustryStandard/Acpi.h>
#include "Coreboot.h"
/**
Convert a packed value from cbuint64 to a UINT64 value.
@param val The pointer to packed data.
@return the UNIT64 value after conversion.
**/
UINT64
cb_unpack64 (
IN struct cbuint64 val
)
{
return LShiftU64 (val.hi, 32) | val.lo;
}
/**
Returns the sum of all elements in a buffer of 16-bit values. During
calculation, the carry bits are also been added.
@param Buffer The pointer to the buffer to carry out the sum operation.
@param Length The size, in bytes, of Buffer.
@return Sum The sum of Buffer with carry bits included during additions.
**/
UINT16
CbCheckSum16 (
IN UINT16 *Buffer,
IN UINTN Length
)
{
UINT32 Sum, TmpValue;
UINTN Idx;
UINT8 *TmpPtr;
Sum = 0;
TmpPtr = (UINT8 *)Buffer;
for(Idx = 0; Idx < Length; Idx++) {
TmpValue = TmpPtr[Idx];
if (Idx % 2 == 1) {
TmpValue <<= 8;
}
Sum += TmpValue;
// Wrap
if (Sum >= 0x10000) {
Sum = (Sum + (Sum >> 16)) & 0xFFFF;
}
}
return (UINT16)((~Sum) & 0xFFFF);
}
/**
Find coreboot record with given Tag from the memory Start in 4096
bytes range.
@param Start The start memory to be searched in
@param Tag The tag id to be found
@retval NULL The Tag is not found.
@retval Others The pointer to the record found.
**/
VOID *
EFIAPI
FindCbTag (
IN VOID *Start,
IN UINT32 Tag
)
{
struct cb_header *Header;
struct cb_record *Record;
UINT8 *TmpPtr;
UINT8 *TagPtr;
UINTN Idx;
UINT16 CheckSum;
Header = NULL;
TmpPtr = (UINT8 *)Start;
for (Idx = 0; Idx < 4096; Idx += 16, TmpPtr += 16) {
Header = (struct cb_header *)TmpPtr;
if (Header->signature == CB_HEADER_SIGNATURE) {
break;
}
}
if (Idx >= 4096) {
return NULL;
}
if ((Header == NULL) || (Header->table_bytes == 0)) {
return NULL;
}
//
// Check the checksum of the coreboot table header
//
CheckSum = CbCheckSum16 ((UINT16 *)Header, sizeof (*Header));
if (CheckSum != 0) {
DEBUG ((EFI_D_ERROR, "Invalid coreboot table header checksum\n"));
return NULL;
}
CheckSum = CbCheckSum16 ((UINT16 *)(TmpPtr + sizeof (*Header)), Header->table_bytes);
if (CheckSum != Header->table_checksum) {
DEBUG ((EFI_D_ERROR, "Incorrect checksum of all the coreboot table entries\n"));
return NULL;
}
TagPtr = NULL;
TmpPtr += Header->header_bytes;
for (Idx = 0; Idx < Header->table_entries; Idx++) {
Record = (struct cb_record *)TmpPtr;
if (Record->tag == CB_TAG_FORWARD) {
TmpPtr = (VOID *)(UINTN)((struct cb_forward *)(UINTN)Record)->forward;
if (Tag == CB_TAG_FORWARD) {
return TmpPtr;
} else {
return FindCbTag (TmpPtr, Tag);
}
}
if (Record->tag == Tag) {
TagPtr = TmpPtr;
break;
}
TmpPtr += Record->size;
}
return TagPtr;
}
/**
Find the given table with TableId from the given coreboot memory Root.
@param Root The coreboot memory table to be searched in
@param TableId Table id to be found
@param pMemTable To save the base address of the memory table found
@param pMemTableSize To save the size of memory table found
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
EFIAPI
FindCbMemTable (
IN struct cbmem_root *Root,
IN UINT32 TableId,
OUT VOID **pMemTable,
OUT UINT32 *pMemTableSize
)
{
UINTN Idx;
BOOLEAN IsImdEntry;
struct cbmem_entry *Entries;
if ((Root == NULL) || (pMemTable == NULL)) {
return RETURN_INVALID_PARAMETER;
}
//
// Check if the entry is CBMEM or IMD
// and handle them separately
//
Entries = Root->entries;
if (Entries[0].magic == CBMEM_ENTRY_MAGIC) {
IsImdEntry = FALSE;
} else {
Entries = (struct cbmem_entry *)((struct imd_root *)Root)->entries;
if (Entries[0].magic == IMD_ENTRY_MAGIC) {
IsImdEntry = TRUE;
} else {
return RETURN_NOT_FOUND;
}
}
for (Idx = 0; Idx < Root->num_entries; Idx++) {
if (Entries[Idx].id == TableId) {
if (IsImdEntry) {
*pMemTable = (VOID *) ((UINTN)Entries[Idx].start + (UINTN)Root);
} else {
*pMemTable = (VOID *) (UINTN)Entries[Idx].start;
}
if (pMemTableSize != NULL) {
*pMemTableSize = Entries[Idx].size;
}
DEBUG ((EFI_D_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
TableId, *pMemTable, Entries[Idx].size));
return RETURN_SUCCESS;
}
}
return RETURN_NOT_FOUND;
}
/**
Acquire the memory information from the coreboot table in memory.
@param MemInfoCallback The callback routine
@param pParam Pointer to the callback routine parameter
@retval RETURN_SUCCESS Successfully find out the memory information.
@retval RETURN_NOT_FOUND Failed to find the memory information.
**/
RETURN_STATUS
EFIAPI
CbParseMemoryInfo (
IN CB_MEM_INFO_CALLBACK MemInfoCallback,
IN VOID *pParam
)
{
struct cb_memory *rec;
struct cb_memory_range *Range;
UINT64 Start;
UINT64 Size;
UINTN Index;
//
// Get the coreboot memory table
//
rec = (struct cb_memory *)FindCbTag (0, CB_TAG_MEMORY);
if (rec == NULL) {
rec = (struct cb_memory *)FindCbTag ((VOID *)(UINTN)PcdGet32 (PcdCbHeaderPointer), CB_TAG_MEMORY);
}
if (rec == NULL) {
return RETURN_NOT_FOUND;
}
for (Index = 0; Index < MEM_RANGE_COUNT(rec); Index++) {
Range = MEM_RANGE_PTR(rec, Index);
Start = cb_unpack64(Range->start);
Size = cb_unpack64(Range->size);
DEBUG ((EFI_D_INFO, "%d. %016lx - %016lx [%02x]\n",
Index, Start, Start + Size - 1, Range->type));
MemInfoCallback (Start, Size, Range->type, pParam);
}
return RETURN_SUCCESS;
}
/**
Acquire the coreboot memory table with the given table id
@param TableId Table id to be searched
@param pMemTable Pointer to the base address of the memory table
@param pMemTableSize Pointer to the size of the memory table
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
EFIAPI
CbParseCbMemTable (
IN UINT32 TableId,
OUT VOID **pMemTable,
OUT UINT32 *pMemTableSize
)
{
struct cb_memory *rec;
struct cb_memory_range *Range;
UINT64 Start;
UINT64 Size;
UINTN Index;
if (pMemTable == NULL) {
return RETURN_INVALID_PARAMETER;
}
*pMemTable = NULL;
//
// Get the coreboot memory table
//
rec = (struct cb_memory *)FindCbTag (0, CB_TAG_MEMORY);
if (rec == NULL) {
rec = (struct cb_memory *)FindCbTag ((VOID *)(UINTN)PcdGet32 (PcdCbHeaderPointer), CB_TAG_MEMORY);
}
if (rec == NULL) {
return RETURN_NOT_FOUND;
}
for (Index = 0; Index < MEM_RANGE_COUNT(rec); Index++) {
Range = MEM_RANGE_PTR(rec, Index);
Start = cb_unpack64(Range->start);
Size = cb_unpack64(Range->size);
if ((Range->type == CB_MEM_TABLE) && (Start > 0x1000)) {
if (FindCbMemTable ((struct cbmem_root *)(UINTN)(Start + Size - DYN_CBMEM_ALIGN_SIZE), TableId, pMemTable, pMemTableSize) == RETURN_SUCCESS)
return RETURN_SUCCESS;
}
}
return RETURN_NOT_FOUND;
}
/**
Acquire the acpi table from coreboot
@param pMemTable Pointer to the base address of the memory table
@param pMemTableSize Pointer to the size of the memory table
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
EFIAPI
CbParseAcpiTable (
OUT VOID **pMemTable,
OUT UINT32 *pMemTableSize
)
{
return CbParseCbMemTable (SIGNATURE_32 ('I', 'P', 'C', 'A'), pMemTable, pMemTableSize);
}
/**
Acquire the smbios table from coreboot
@param pMemTable Pointer to the base address of the memory table
@param pMemTableSize Pointer to the size of the memory table
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
EFIAPI
CbParseSmbiosTable (
OUT VOID **pMemTable,
OUT UINT32 *pMemTableSize
)
{
return CbParseCbMemTable (SIGNATURE_32 ('T', 'B', 'M', 'S'), pMemTable, pMemTableSize);
}
/**
Find the required fadt information
@param pPmCtrlReg Pointer to the address of power management control register
@param pPmTimerReg Pointer to the address of power management timer register
@param pResetReg Pointer to the address of system reset register
@param pResetValue Pointer to the value to be written to the system reset register
@param pPmEvtReg Pointer to the address of power management event register
@param pPmGpeEnReg Pointer to the address of power management GPE enable register
@retval RETURN_SUCCESS Successfully find out all the required fadt information.
@retval RETURN_NOT_FOUND Failed to find the fadt table.
**/
RETURN_STATUS
EFIAPI
CbParseFadtInfo (
OUT UINTN *pPmCtrlReg,
OUT UINTN *pPmTimerReg,
OUT UINTN *pResetReg,
OUT UINTN *pResetValue,
OUT UINTN *pPmEvtReg,
OUT UINTN *pPmGpeEnReg
)
{
EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp;
EFI_ACPI_DESCRIPTION_HEADER *Rsdt;
UINT32 *Entry32;
UINTN Entry32Num;
EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
EFI_ACPI_DESCRIPTION_HEADER *Xsdt;
UINT64 *Entry64;
UINTN Entry64Num;
UINTN Idx;
RETURN_STATUS Status;
Rsdp = NULL;
Status = RETURN_SUCCESS;
Status = CbParseAcpiTable ((VOID **)&Rsdp, NULL);
if (RETURN_ERROR(Status)) {
return Status;
}
if (Rsdp == NULL) {
return RETURN_NOT_FOUND;
}
DEBUG ((EFI_D_INFO, "Find Rsdp at %p\n", Rsdp));
DEBUG ((EFI_D_INFO, "Find Rsdt 0x%x, Xsdt 0x%lx\n", Rsdp->RsdtAddress, Rsdp->XsdtAddress));
//
// Search Rsdt First
//
Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->RsdtAddress);
if (Rsdt != NULL) {
Entry32 = (UINT32 *)(Rsdt + 1);
Entry32Num = (Rsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 2;
for (Idx = 0; Idx < Entry32Num; Idx++) {
if (*(UINT32 *)(UINTN)(Entry32[Idx]) == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)(UINTN)(Entry32[Idx]);
if (pPmCtrlReg != NULL) {
*pPmCtrlReg = Fadt->Pm1aCntBlk;
}
DEBUG ((EFI_D_INFO, "PmCtrl Reg 0x%x\n", Fadt->Pm1aCntBlk));
if (pPmTimerReg != NULL) {
*pPmTimerReg = Fadt->PmTmrBlk;
}
DEBUG ((EFI_D_INFO, "PmTimer Reg 0x%x\n", Fadt->PmTmrBlk));
if (pResetReg != NULL) {
*pResetReg = (UINTN)Fadt->ResetReg.Address;
}
DEBUG ((EFI_D_INFO, "Reset Reg 0x%lx\n", Fadt->ResetReg.Address));
if (pResetValue != NULL) {
*pResetValue = Fadt->ResetValue;
}
DEBUG ((EFI_D_INFO, "Reset Value 0x%x\n", Fadt->ResetValue));
if (pPmEvtReg != NULL) {
*pPmEvtReg = Fadt->Pm1aEvtBlk;
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));
}
if (pPmGpeEnReg != NULL) {
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));
}
//
// Verify values for proper operation
//
ASSERT(Fadt->Pm1aCntBlk != 0);
ASSERT(Fadt->PmTmrBlk != 0);
ASSERT(Fadt->ResetReg.Address != 0);
ASSERT(Fadt->Pm1aEvtBlk != 0);
ASSERT(Fadt->Gpe0Blk != 0);
DEBUG_CODE_BEGIN ();
BOOLEAN SciEnabled;
//
// Check the consistency of SCI enabling
//
//
// Get SCI_EN value
//
if (Fadt->Pm1CntLen == 4) {
SciEnabled = (IoRead32 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;
} else {
//
// if (Pm1CntLen == 2), use 16 bit IO read;
// if (Pm1CntLen != 2 && Pm1CntLen != 4), use 16 bit IO read as a fallback
//
SciEnabled = (IoRead16 (Fadt->Pm1aCntBlk) & BIT0)? TRUE : FALSE;
}
if (!(Fadt->Flags & EFI_ACPI_5_0_HW_REDUCED_ACPI) &&
(Fadt->SmiCmd == 0) &&
!SciEnabled) {
//
// The ACPI enabling status is inconsistent: SCI is not enabled but ACPI
// table does not provide a means to enable it through FADT->SmiCmd
//
DEBUG ((DEBUG_ERROR, "ERROR: The ACPI enabling status is inconsistent: SCI is not"
" enabled but the ACPI table does not provide a means to enable it through FADT->SmiCmd."
" This may cause issues in OS.\n"));
ASSERT (FALSE);
}
DEBUG_CODE_END ();
return RETURN_SUCCESS;
}
}
}
//
// Search Xsdt Second
//
Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)(Rsdp->XsdtAddress);
if (Xsdt != NULL) {
Entry64 = (UINT64 *)(Xsdt + 1);
Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3;
for (Idx = 0; Idx < Entry64Num; Idx++) {
if (*(UINT32 *)(UINTN)(Entry64[Idx]) == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) {
Fadt = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *)(UINTN)(Entry64[Idx]);
if (pPmCtrlReg)
*pPmCtrlReg = Fadt->Pm1aCntBlk;
DEBUG ((EFI_D_ERROR, "PmCtrl Reg 0x%x\n", Fadt->Pm1aCntBlk));
if (pPmTimerReg)
*pPmTimerReg = Fadt->PmTmrBlk;
DEBUG ((EFI_D_ERROR, "PmTimer Reg 0x%x\n", Fadt->PmTmrBlk));
if (pResetReg)
*pResetReg = (UINTN)Fadt->ResetReg.Address;
DEBUG ((EFI_D_ERROR, "Reset Reg 0x%lx\n", Fadt->ResetReg.Address));
if (pResetValue)
*pResetValue = Fadt->ResetValue;
DEBUG ((EFI_D_ERROR, "Reset Value 0x%x\n", Fadt->ResetValue));
if (pPmEvtReg != NULL) {
*pPmEvtReg = Fadt->Pm1aEvtBlk;
DEBUG ((EFI_D_INFO, "PmEvt Reg 0x%x\n", Fadt->Pm1aEvtBlk));
}
if (pPmGpeEnReg != NULL) {
*pPmGpeEnReg = Fadt->Gpe0Blk + Fadt->Gpe0BlkLen / 2;
DEBUG ((EFI_D_INFO, "PmGpeEn Reg 0x%x\n", *pPmGpeEnReg));
}
return RETURN_SUCCESS;
}
}
}
return RETURN_NOT_FOUND;
}
/**
Find the serial port information
@param pRegBase Pointer to the base address of serial port registers
@param pRegAccessType Pointer to the access type of serial port registers
@param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate
@param pInputHertz Pointer to the input clock frequency
@param pUartPciAddr Pointer to the UART PCI bus, dev and func address
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
**/
RETURN_STATUS
EFIAPI
CbParseSerialInfo (
OUT UINT32 *pRegBase,
OUT UINT32 *pRegAccessType,
OUT UINT32 *pRegWidth,
OUT UINT32 *pBaudrate,
OUT UINT32 *pInputHertz,
OUT UINT32 *pUartPciAddr
)
{
struct cb_serial *CbSerial;
CbSerial = FindCbTag (0, CB_TAG_SERIAL);
if (CbSerial == NULL) {
CbSerial = FindCbTag ((VOID *)(UINTN)PcdGet32 (PcdCbHeaderPointer), CB_TAG_SERIAL);
}
if (CbSerial == NULL) {
return RETURN_NOT_FOUND;
}
if (pRegBase != NULL) {
*pRegBase = CbSerial->baseaddr;
}
if (pRegWidth != NULL) {
*pRegWidth = CbSerial->regwidth;
}
if (pRegAccessType != NULL) {
*pRegAccessType = CbSerial->type;
}
if (pBaudrate != NULL) {
*pBaudrate = CbSerial->baud;
}
if (pInputHertz != NULL) {
*pInputHertz = CbSerial->input_hertz;
}
if (pUartPciAddr != NULL) {
*pUartPciAddr = CbSerial->uart_pci_addr;
}
return RETURN_SUCCESS;
}
/**
Search for the coreboot table header
@param Level Level of the search depth
@param HeaderPtr Pointer to the pointer of coreboot table header
@retval RETURN_SUCCESS Successfully find the coreboot table header .
@retval RETURN_NOT_FOUND Failed to find the coreboot table header .
**/
RETURN_STATUS
EFIAPI
CbParseGetCbHeader (
IN UINTN Level,
OUT VOID **HeaderPtr
)
{
UINTN Index;
VOID *TempPtr;
if (HeaderPtr == NULL) {
return RETURN_NOT_FOUND;
}
TempPtr = NULL;
for (Index = 0; Index < Level; Index++) {
TempPtr = FindCbTag (TempPtr, CB_TAG_FORWARD);
if (TempPtr == NULL) {
break;
}
}
if ((Index >= Level) && (TempPtr != NULL)) {
*HeaderPtr = TempPtr;
return RETURN_SUCCESS;
}
return RETURN_NOT_FOUND;
}
/**
Find the video frame buffer information
@param pFbInfo Pointer to the FRAME_BUFFER_INFO structure
@retval RETURN_SUCCESS Successfully find the video frame buffer information.
@retval RETURN_NOT_FOUND Failed to find the video frame buffer information .
**/
RETURN_STATUS
EFIAPI
CbParseFbInfo (
OUT FRAME_BUFFER_INFO *pFbInfo
)
{
struct cb_framebuffer *CbFbRec;
if (pFbInfo == NULL) {
return RETURN_INVALID_PARAMETER;
}
CbFbRec = FindCbTag (0, CB_TAG_FRAMEBUFFER);
if (CbFbRec == NULL) {
CbFbRec = FindCbTag ((VOID *)(UINTN)PcdGet32 (PcdCbHeaderPointer), CB_TAG_FRAMEBUFFER);
}
if (CbFbRec == NULL) {
return RETURN_NOT_FOUND;
}
DEBUG ((EFI_D_INFO, "Found coreboot video frame buffer information\n"));
DEBUG ((EFI_D_INFO, "physical_address: 0x%lx\n", CbFbRec->physical_address));
DEBUG ((EFI_D_INFO, "x_resolution: 0x%x\n", CbFbRec->x_resolution));
DEBUG ((EFI_D_INFO, "y_resolution: 0x%x\n", CbFbRec->y_resolution));
DEBUG ((EFI_D_INFO, "bits_per_pixel: 0x%x\n", CbFbRec->bits_per_pixel));
DEBUG ((EFI_D_INFO, "bytes_per_line: 0x%x\n", CbFbRec->bytes_per_line));
DEBUG ((EFI_D_INFO, "red_mask_size: 0x%x\n", CbFbRec->red_mask_size));
DEBUG ((EFI_D_INFO, "red_mask_pos: 0x%x\n", CbFbRec->red_mask_pos));
DEBUG ((EFI_D_INFO, "green_mask_size: 0x%x\n", CbFbRec->green_mask_size));
DEBUG ((EFI_D_INFO, "green_mask_pos: 0x%x\n", CbFbRec->green_mask_pos));
DEBUG ((EFI_D_INFO, "blue_mask_size: 0x%x\n", CbFbRec->blue_mask_size));
DEBUG ((EFI_D_INFO, "blue_mask_pos: 0x%x\n", CbFbRec->blue_mask_pos));
DEBUG ((EFI_D_INFO, "reserved_mask_size: 0x%x\n", CbFbRec->reserved_mask_size));
DEBUG ((EFI_D_INFO, "reserved_mask_pos: 0x%x\n", CbFbRec->reserved_mask_pos));
pFbInfo->LinearFrameBuffer = CbFbRec->physical_address;
pFbInfo->HorizontalResolution = CbFbRec->x_resolution;
pFbInfo->VerticalResolution = CbFbRec->y_resolution;
pFbInfo->BitsPerPixel = CbFbRec->bits_per_pixel;
pFbInfo->BytesPerScanLine = (UINT16)CbFbRec->bytes_per_line;
pFbInfo->Red.Mask = (1 << CbFbRec->red_mask_size) - 1;
pFbInfo->Red.Position = CbFbRec->red_mask_pos;
pFbInfo->Green.Mask = (1 << CbFbRec->green_mask_size) - 1;
pFbInfo->Green.Position = CbFbRec->green_mask_pos;
pFbInfo->Blue.Mask = (1 << CbFbRec->blue_mask_size) - 1;
pFbInfo->Blue.Position = CbFbRec->blue_mask_pos;
pFbInfo->Reserved.Mask = (1 << CbFbRec->reserved_mask_size) - 1;
pFbInfo->Reserved.Position = CbFbRec->reserved_mask_pos;
return RETURN_SUCCESS;
}

39
CorebootModulePkg/Library/CbParseLib/CbParseLib.inf
View File

@ -1,39 +0,0 @@
## @file
# Coreboot Table Parse Library.
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CbParseLib
FILE_GUID = 49EDFC9E-5945-4386-9C0B-C9B60CD45BB1
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CbParseLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
CbParseLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
CorebootModulePkg/CorebootModulePkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
IoLib
DebugLib
PcdLib
[Pcd]
gUefiCorebootModulePkgTokenSpaceGuid.PcdCbHeaderPointer

29
CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.c
View File

@ -1,29 +0,0 @@
/** @file
Include all platform specific features which can be customized by IBV/OEM.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/UefiLib.h>
#include <Library/CbPlatformSupportLib.h>
/**
Parse platform specific information from coreboot.
@retval RETURN_SUCCESS The platform specific coreboot support succeeded.
@retval RETURN_DEVICE_ERROR The platform specific coreboot support could not be completed.
**/
EFI_STATUS
EFIAPI
CbParsePlatformInfo (
VOID
)
{
return EFI_SUCCESS;
}

29
CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.inf
View File

@ -1,29 +0,0 @@
## @file
# Include all platform specific features which can be customized by IBV/OEM.
#
# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CbPlatformSupportLib
MODULE_UNI_FILE = CbPlatformSupportLibNull.uni
FILE_GUID = B42AA265-00CA-4d4b-AC14-DBD5268E1BC7
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = CbPlatformSupportLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
CbPlatformSupportLibNull.c
[Packages]
MdePkg/MdePkg.dec
CorebootModulePkg/CorebootModulePkg.dec

14
CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.uni
View File

@ -1,14 +0,0 @@
// /** @file
// NULL implementation for CbPlatformSupportLib library class interfaces.
//
// Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
// **/
#string STR_MODULE_ABSTRACT #language en-US "NULL implementation for CbPlatformSupportLib library class interfaces"
#string STR_MODULE_DESCRIPTION #language en-US "NULL implementation for CbPlatformSupportLib library class interfaces."

170
CorebootModulePkg/SataControllerDxe/ComponentName.c
View File

@ -1,170 +0,0 @@
/** @file
UEFI Component Name(2) protocol implementation for Sata Controller driver.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SataController.h"
//
/// EFI Component Name Protocol
///
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName = {
SataControllerComponentNameGetDriverName,
SataControllerComponentNameGetControllerName,
"eng"
};
//
/// EFI Component Name 2 Protocol
///
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SataControllerComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) SataControllerComponentNameGetControllerName,
"en"
};
//
/// Driver Name Strings
///
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerDriverNameTable[] = {
{
"eng;en",
(CHAR16 *)L"Sata Controller Init Driver"
},
{
NULL,
NULL
}
};
///
/// Controller Name Strings
///
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSataControllerControllerNameTable[] = {
{
"eng;en",
(CHAR16 *)L"Sata Controller"
},
{
NULL,
NULL
}
};
/**
Retrieves a Unicode string that is the user readable name of the UEFI Driver.
@param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
@param Language A pointer to a three character ISO 639-2 language identifier.
This is the language of the driver name that that the caller
is requesting, and it must match one of the languages specified
in SupportedLanguages. The number of languages supported by a
driver is up to the driver writer.
@param DriverName A pointer to the Unicode string to return. This Unicode string
is the name of the driver specified by This in the language
specified by Language.
@retval EFI_SUCCESS The Unicode string for the Driver specified by This
and the language specified by Language was returned
in DriverName.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER DriverName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This does not support the
language specified by Language.
**/
EFI_STATUS
EFIAPI
SataControllerComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
Language,
This->SupportedLanguages,
mSataControllerDriverNameTable,
DriverName,
(BOOLEAN)(This == &gSataControllerComponentName)
);
}
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by an UEFI Driver.
@param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
@param ControllerHandle The handle of a controller that the driver specified by
This is managing. This handle specifies the controller
whose name is to be returned.
@param ChildHandle OPTIONAL The handle of the child controller to retrieve the name
of. This is an optional parameter that may be NULL. It
will be NULL for device drivers. It will also be NULL
for a bus drivers that wish to retrieve the name of the
bus controller. It will not be NULL for a bus driver
that wishes to retrieve the name of a child controller.
@param Language A pointer to a three character ISO 639-2 language
identifier. This is the language of the controller name
that that the caller is requesting, and it must match one
of the languages specified in SupportedLanguages. The
number of languages supported by a driver is up to the
driver writer.
@param ControllerName A pointer to the Unicode string to return. This Unicode
string is the name of the controller specified by
ControllerHandle and ChildHandle in the language
specified by Language from the point of view of the
driver specified by This.
@retval EFI_SUCCESS The Unicode string for the user readable name in the
language specified by Language for the driver
specified by This was returned in DriverName.
@retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
@retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
EFI_HANDLE.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER ControllerName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This is not currently
managing the controller specified by
ControllerHandle and ChildHandle.
@retval EFI_UNSUPPORTED The driver specified by This does not support the
language specified by Language.
**/
EFI_STATUS
EFIAPI
SataControllerComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
EFI_STATUS Status;
//
// Make sure this driver is currently managing ControllHandle
//
Status = EfiTestManagedDevice (
ControllerHandle,
gSataControllerDriverBinding.DriverBindingHandle,
&gEfiPciIoProtocolGuid
);
if (EFI_ERROR (Status)) {
return Status;
}
if (ChildHandle != NULL) {
return EFI_UNSUPPORTED;
}
return LookupUnicodeString2 (
Language,
This->SupportedLanguages,
mSataControllerControllerNameTable,
ControllerName,
(BOOLEAN)(This == &gSataControllerComponentName)
);
}

1043
CorebootModulePkg/SataControllerDxe/SataController.c
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536
CorebootModulePkg/SataControllerDxe/SataController.h
View File

@ -1,536 +0,0 @@
/** @file
Header file for Sata Controller driver.
Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _SATA_CONTROLLER_H_
#define _SATA_CONTROLLER_H_
#include <Uefi.h>
#include <Protocol/ComponentName.h>
#include <Protocol/DriverBinding.h>
#include <Protocol/PciIo.h>
#include <Protocol/IdeControllerInit.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/DebugLib.h>
#include <Library/UefiLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <IndustryStandard/Pci.h>
//
// Global Variables definitions
//
extern EFI_DRIVER_BINDING_PROTOCOL gSataControllerDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gSataControllerComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gSataControllerComponentName2;
#define AHCI_BAR_INDEX 0x05
#define R_AHCI_CAP 0x0
#define B_AHCI_CAP_NPS (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) // Number of Ports
#define B_AHCI_CAP_SPM BIT17 // Supports Port Multiplier
///
/// AHCI each channel can have up to 1 device
///
#define AHCI_MAX_DEVICES 0x01
///
/// AHCI each channel can have 15 devices in the presence of a multiplier
///
#define AHCI_MULTI_MAX_DEVICES 0x0F
///
/// IDE supports 2 channel max
///
#define IDE_MAX_CHANNEL 0x02
///
/// IDE supports 2 devices max
///
#define IDE_MAX_DEVICES 0x02
#define SATA_ENUMER_ALL FALSE
//
// Sata Controller driver private data structure
//
#define SATA_CONTROLLER_SIGNATURE SIGNATURE_32('S','A','T','A')
typedef struct _EFI_SATA_CONTROLLER_PRIVATE_DATA {
//
// Standard signature used to identify Sata Controller private data
//
UINT32 Signature;
//
// Protocol instance of IDE_CONTROLLER_INIT produced by this driver
//
EFI_IDE_CONTROLLER_INIT_PROTOCOL IdeInit;
//
// Copy of protocol pointers used by this driver
//
EFI_PCI_IO_PROTOCOL *PciIo;
//
// The number of devices that are supported by this channel
//
UINT8 DeviceCount;
//
// The highest disqualified mode for each attached device,
// From ATA/ATAPI spec, if a mode is not supported,
// the modes higher than it is also not supported
//
EFI_ATA_COLLECTIVE_MODE *DisqualifiedModes;
//
// A copy of EFI_IDENTIFY_DATA data for each attached SATA device and its flag
//
EFI_IDENTIFY_DATA *IdentifyData;
BOOLEAN *IdentifyValid;
} EFI_SATA_CONTROLLER_PRIVATE_DATA;
#define SATA_CONTROLLER_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_SATA_CONTROLLER_PRIVATE_DATA, IdeInit, SATA_CONTROLLER_SIGNATURE)
//
// Driver binding functions declaration
//
/**
Supported function of Driver Binding protocol for this driver.
Test to see if this driver supports ControllerHandle.
@param This Protocol instance pointer.
@param Controller Handle of device to test.
@param RemainingDevicePath A pointer to the device path. Should be ignored by
device driver.
@retval EFI_SUCCESS This driver supports this device.
@retval EFI_ALREADY_STARTED This driver is already running on this device.
@retval other This driver does not support this device.
**/
EFI_STATUS
EFIAPI
SataControllerSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
;
/**
This routine is called right after the .Supported() called and
Start this driver on ControllerHandle.
@param This Protocol instance pointer.
@param Controller Handle of device to bind driver to.
@param RemainingDevicePath A pointer to the device path. Should be ignored by
device driver.
@retval EFI_SUCCESS This driver is added to this device.
@retval EFI_ALREADY_STARTED This driver is already running on this device.
@retval other Some error occurs when binding this driver to this device.
**/
EFI_STATUS
EFIAPI
SataControllerStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
)
;
/**
Stop this driver on ControllerHandle.
@param This Protocol instance pointer.
@param Controller Handle of device to stop driver on.
@param NumberOfChildren Not used.
@param ChildHandleBuffer Not used.
@retval EFI_SUCCESS This driver is removed from this device.
@retval other Some error occurs when removing this driver from this device.
**/
EFI_STATUS
EFIAPI
SataControllerStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
)
;
//
// IDE controller init functions declaration
//
/**
Returns the information about the specified IDE channel.
This function can be used to obtain information about a particular IDE channel.
The driver entity uses this information during the enumeration process.
If Enabled is set to FALSE, the driver entity will not scan the channel. Note
that it will not prevent an operating system driver from scanning the channel.
For most of today's controllers, MaxDevices will either be 1 or 2. For SATA
controllers, this value will always be 1. SATA configurations can contain SATA
port multipliers. SATA port multipliers behave like SATA bridges and can support
up to 16 devices on the other side. If a SATA port out of the IDE controller
is connected to a port multiplier, MaxDevices will be set to the number of SATA
devices that the port multiplier supports. Because today's port multipliers
support up to fifteen SATA devices, this number can be as large as fifteen. The IDE
bus driver is required to scan for the presence of port multipliers behind an SATA
controller and enumerate up to MaxDevices number of devices behind the port
multiplier.
In this context, the devices behind a port multiplier constitute a channel.
@param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
@param[in] Channel Zero-based channel number.
@param[out] Enabled TRUE if this channel is enabled. Disabled channels
are not scanned to see if any devices are present.
@param[out] MaxDevices The maximum number of IDE devices that the bus driver
can expect on this channel. For the ATA/ATAPI
specification, version 6, this number will either be
one or two. For Serial ATA (SATA) configurations with a
port multiplier, this number can be as large as fifteen.
@retval EFI_SUCCESS Information was returned without any errors.
@retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
**/
EFI_STATUS
EFIAPI
IdeInitGetChannelInfo (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
OUT BOOLEAN *Enabled,
OUT UINT8 *MaxDevices
)
;
/**
The notifications from the driver entity that it is about to enter a certain
phase of the IDE channel enumeration process.
This function can be used to notify the IDE controller driver to perform
specific actions, including any chipset-specific initialization, so that the
chipset is ready to enter the next phase. Seven notification points are defined
at this time.
More synchronization points may be added as required in the future.
@param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
@param[in] Phase The phase during enumeration.
@param[in] Channel Zero-based channel number.
@retval EFI_SUCCESS The notification was accepted without any errors.
@retval EFI_UNSUPPORTED Phase is not supported.
@retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
@retval EFI_NOT_READY This phase cannot be entered at this time; for
example, an attempt was made to enter a Phase
without having entered one or more previous
Phase.
**/
EFI_STATUS
EFIAPI
IdeInitNotifyPhase (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN EFI_IDE_CONTROLLER_ENUM_PHASE Phase,
IN UINT8 Channel
)
;
/**
Submits the device information to the IDE controller driver.
This function is used by the driver entity to pass detailed information about
a particular device to the IDE controller driver. The driver entity obtains
this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData
is the pointer to the response data buffer. The IdentifyData buffer is owned
by the driver entity, and the IDE controller driver must make a local copy
of the entire buffer or parts of the buffer as needed. The original IdentifyData
buffer pointer may not be valid when
- EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or
- EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point.
The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to
compute the optimum mode for the device. These fields are not limited to the
timing information. For example, an implementation of the IDE controller driver
may examine the vendor and type/mode field to match known bad drives.
The driver entity may submit drive information in any order, as long as it
submits information for all the devices belonging to the enumeration group
before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device
in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
should be called with IdentifyData set to NULL. The IDE controller driver may
not have any other mechanism to know whether a device is present or not. Therefore,
setting IdentifyData to NULL does not constitute an error condition.
EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a
given (Channel, Device) pair.
@param[in] This A pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
@param[in] Channel Zero-based channel number.
@param[in] Device Zero-based device number on the Channel.
@param[in] IdentifyData The device's response to the ATA IDENTIFY_DEVICE command.
@retval EFI_SUCCESS The information was accepted without any errors.
@retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
@retval EFI_INVALID_PARAMETER Device is invalid.
**/
EFI_STATUS
EFIAPI
IdeInitSubmitData (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_IDENTIFY_DATA *IdentifyData
)
;
/**
Disqualifies specific modes for an IDE device.
This function allows the driver entity or other drivers (such as platform
drivers) to reject certain timing modes and request the IDE controller driver
to recalculate modes. This function allows the driver entity and the IDE
controller driver to negotiate the timings on a per-device basis. This function
is useful in the case of drives that lie about their capabilities. An example
is when the IDE device fails to accept the timing modes that are calculated
by the IDE controller driver based on the response to the Identify Drive command.
If the driver entity does not want to limit the ATA timing modes and leave that
decision to the IDE controller driver, it can either not call this function for
the given device or call this function and set the Valid flag to FALSE for all
modes that are listed in EFI_ATA_COLLECTIVE_MODE.
The driver entity may disqualify modes for a device in any order and any number
of times.
This function can be called multiple times to invalidate multiple modes of the
same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI
specification for more information on PIO modes.
For Serial ATA (SATA) controllers, this member function can be used to disqualify
a higher transfer rate mode on a given channel. For example, a platform driver
may inform the IDE controller driver to not use second-generation (Gen2) speeds
for a certain SATA drive.
@param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
@param[in] Channel The zero-based channel number.
@param[in] Device The zero-based device number on the Channel.
@param[in] BadModes The modes that the device does not support and that
should be disqualified.
@retval EFI_SUCCESS The modes were accepted without any errors.
@retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
@retval EFI_INVALID_PARAMETER Device is invalid.
@retval EFI_INVALID_PARAMETER IdentifyData is NULL.
**/
EFI_STATUS
EFIAPI
IdeInitDisqualifyMode (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *BadModes
)
;
/**
Returns the information about the optimum modes for the specified IDE device.
This function is used by the driver entity to obtain the optimum ATA modes for
a specific device. The IDE controller driver takes into account the following
while calculating the mode:
- The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
- The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()
The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
for all the devices that belong to an enumeration group before calling
EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group.
The IDE controller driver will use controller- and possibly platform-specific
algorithms to arrive at SupportedModes. The IDE controller may base its
decision on user preferences and other considerations as well. This function
may be called multiple times because the driver entity may renegotiate the mode
with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode().
The driver entity may collect timing information for various devices in any
order. The driver entity is responsible for making sure that all the dependencies
are satisfied. For example, the SupportedModes information for device A that
was previously returned may become stale after a call to
EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B.
The buffer SupportedModes is allocated by the callee because the caller does
not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE
is defined in a way that allows for future extensibility and can be of variable
length. This memory pool should be deallocated by the caller when it is no
longer necessary.
The IDE controller driver for a Serial ATA (SATA) controller can use this
member function to force a lower speed (first-generation [Gen1] speeds on a
second-generation [Gen2]-capable hardware). The IDE controller driver can
also allow the driver entity to stay with the speed that has been negotiated
by the physical layer.
@param[in] This The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
@param[in] Channel A zero-based channel number.
@param[in] Device A zero-based device number on the Channel.
@param[out] SupportedModes The optimum modes for the device.
@retval EFI_SUCCESS SupportedModes was returned.
@retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
@retval EFI_INVALID_PARAMETER Device is invalid.
@retval EFI_INVALID_PARAMETER SupportedModes is NULL.
@retval EFI_NOT_READY Modes cannot be calculated due to a lack of
data. This error may happen if
EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData()
were not called for at least one drive in the
same enumeration group.
**/
EFI_STATUS
EFIAPI
IdeInitCalculateMode (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
OUT EFI_ATA_COLLECTIVE_MODE **SupportedModes
)
;
/**
Commands the IDE controller driver to program the IDE controller hardware
so that the specified device can operate at the specified mode.
This function is used by the driver entity to instruct the IDE controller
driver to program the IDE controller hardware to the specified modes. This
function can be called only once for a particular device. For a Serial ATA
(SATA) Advanced Host Controller Interface (AHCI) controller, no controller-
specific programming may be required.
@param[in] This Pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
@param[in] Channel Zero-based channel number.
@param[in] Device Zero-based device number on the Channel.
@param[in] Modes The modes to set.
@retval EFI_SUCCESS The command was accepted without any errors.
@retval EFI_INVALID_PARAMETER Channel is invalid (Channel >= ChannelCount).
@retval EFI_INVALID_PARAMETER Device is invalid.
@retval EFI_NOT_READY Modes cannot be set at this time due to lack of data.
@retval EFI_DEVICE_ERROR Modes cannot be set due to hardware failure.
The driver entity should not use this device.
**/
EFI_STATUS
EFIAPI
IdeInitSetTiming (
IN EFI_IDE_CONTROLLER_INIT_PROTOCOL *This,
IN UINT8 Channel,
IN UINT8 Device,
IN EFI_ATA_COLLECTIVE_MODE *Modes
)
;
//
// Forward reference declaration
//
/**
Retrieves a Unicode string that is the user readable name of the UEFI Driver.
@param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
@param Language A pointer to a three character ISO 639-2 language identifier.
This is the language of the driver name that that the caller
is requesting, and it must match one of the languages specified
in SupportedLanguages. The number of languages supported by a
driver is up to the driver writer.
@param DriverName A pointer to the Unicode string to return. This Unicode string
is the name of the driver specified by This in the language
specified by Language.
@retval EFI_SUCCESS The Unicode string for the Driver specified by This
and the language specified by Language was returned
in DriverName.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER DriverName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This does not support the
language specified by Language.
**/
EFI_STATUS
EFIAPI
SataControllerComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
)
;
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by an UEFI Driver.
@param This A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
@param ControllerHandle The handle of a controller that the driver specified by
This is managing. This handle specifies the controller
whose name is to be returned.
@param OPTIONAL ChildHandle The handle of the child controller to retrieve the name
of. This is an optional parameter that may be NULL. It
will be NULL for device drivers. It will also be NULL
for a bus drivers that wish to retrieve the name of the
bus controller. It will not be NULL for a bus driver
that wishes to retrieve the name of a child controller.
@param Language A pointer to a three character ISO 639-2 language
identifier. This is the language of the controller name
that that the caller is requesting, and it must match one
of the languages specified in SupportedLanguages. The
number of languages supported by a driver is up to the
driver writer.
@param ControllerName A pointer to the Unicode string to return. This Unicode
string is the name of the controller specified by
ControllerHandle and ChildHandle in the language
specified by Language from the point of view of the
driver specified by This.
@retval EFI_SUCCESS The Unicode string for the user readable name in the
language specified by Language for the driver
specified by This was returned in DriverName.
@retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE.
@retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
EFI_HANDLE.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER ControllerName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This is not currently
managing the controller specified by
ControllerHandle and ChildHandle.
@retval EFI_UNSUPPORTED The driver specified by This does not support the
language specified by Language.
**/
EFI_STATUS
EFIAPI
SataControllerComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
;
#endif

43
CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf
View File

@ -1,43 +0,0 @@
## @file
#
# Component description file for the Sata Controller driver.
#
# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SataController
FILE_GUID = 8F4CD826-A5A0-4e93-9522-CFB0AB72926C
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = InitializeSataControllerDriver
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
ComponentName.c
SataController.c
SataController.h
[Packages]
MdePkg/MdePkg.dec
[LibraryClasses]
UefiDriverEntryPoint
DebugLib
UefiLib
BaseLib
BaseMemoryLib
MemoryAllocationLib
UefiBootServicesTableLib
[Protocols]
gEfiPciIoProtocolGuid
gEfiIdeControllerInitProtocolGuid

193
CorebootModulePkg/SecCore/FindPeiCore.c
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@ -1,193 +0,0 @@
/** @file
Locate the entry point for the PEI Core
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/BaseLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include "SecMain.h"
/**
Find core image base.
@param BootFirmwareVolumePtr Point to the boot firmware volume.
@param SecCoreImageBase The base address of the SEC core image.
@param PeiCoreImageBase The base address of the PEI core image.
**/
EFI_STATUS
EFIAPI
FindImageBase (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase,
OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
)
{
EFI_PHYSICAL_ADDRESS CurrentAddress;
EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
EFI_FFS_FILE_HEADER *File;
UINT32 Size;
EFI_PHYSICAL_ADDRESS EndOfFile;
EFI_COMMON_SECTION_HEADER *Section;
EFI_PHYSICAL_ADDRESS EndOfSection;
*SecCoreImageBase = 0;
*PeiCoreImageBase = 0;
CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) BootFirmwareVolumePtr;
EndOfFirmwareVolume = CurrentAddress + BootFirmwareVolumePtr->FvLength;
//
// Loop through the FFS files in the Boot Firmware Volume
//
for (EndOfFile = CurrentAddress + BootFirmwareVolumePtr->HeaderLength; ; ) {
CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;
if (CurrentAddress > EndOfFirmwareVolume) {
return EFI_NOT_FOUND;
}
File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
if (IS_FFS_FILE2 (File)) {
Size = FFS_FILE2_SIZE (File);
if (Size <= 0x00FFFFFF) {
return EFI_NOT_FOUND;
}
} else {
Size = FFS_FILE_SIZE (File);
if (Size < sizeof (EFI_FFS_FILE_HEADER)) {
return EFI_NOT_FOUND;
}
}
EndOfFile = CurrentAddress + Size;
if (EndOfFile > EndOfFirmwareVolume) {
return EFI_NOT_FOUND;
}
//
// Look for SEC Core / PEI Core files
//
if (File->Type != EFI_FV_FILETYPE_SECURITY_CORE &&
File->Type != EFI_FV_FILETYPE_PEI_CORE) {
continue;
}
//
// Loop through the FFS file sections within the FFS file
//
if (IS_FFS_FILE2 (File)) {
EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));
} else {
EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));
}
for (;;) {
CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;
Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;
if (IS_SECTION2 (Section)) {
Size = SECTION2_SIZE (Section);
if (Size <= 0x00FFFFFF) {
return EFI_NOT_FOUND;
}
} else {
Size = SECTION_SIZE (Section);
if (Size < sizeof (EFI_COMMON_SECTION_HEADER)) {
return EFI_NOT_FOUND;
}
}
EndOfSection = CurrentAddress + Size;
if (EndOfSection > EndOfFile) {
return EFI_NOT_FOUND;
}
//
// Look for executable sections
//
if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {
if (File->Type == EFI_FV_FILETYPE_SECURITY_CORE) {
if (IS_SECTION2 (Section)) {
*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));
} else {
*SecCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));
}
} else {
if (IS_SECTION2 (Section)) {
*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));
} else {
*PeiCoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));
}
}
break;
}
}
//
// Both SEC Core and PEI Core images found
//
if (*SecCoreImageBase != 0 && *PeiCoreImageBase != 0) {
return EFI_SUCCESS;
}
}
}
/**
Find and return Pei Core entry point.
It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param BootFirmwareVolumePtr Point to the boot firmware volume.
@param PeiCoreEntryPoint The entry point of the PEI core.
**/
VOID
EFIAPI
FindAndReportEntryPoints (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
)
{
EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS SecCoreImageBase;
EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
//
// Find SEC Core and PEI Core image base
//
Status = FindImageBase (BootFirmwareVolumePtr, &SecCoreImageBase, &PeiCoreImageBase);
ASSERT_EFI_ERROR (Status);
ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));
//
// Report SEC Core debug information when remote debug is enabled
//
ImageContext.ImageAddress = SecCoreImageBase;
ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
//
// Report PEI Core debug information when remote debug is enabled
//
ImageContext.ImageAddress = PeiCoreImageBase;
ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
//
// Find PEI Core entry point
//
Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);
if (EFI_ERROR (Status)) {
*PeiCoreEntryPoint = 0;
}
return;
}

72
CorebootModulePkg/SecCore/Ia32/SecEntry.asm
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@ -1,72 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; SecEntry.asm
;
; Abstract:
;
; This is the code that begins in protected mode.
; It will transfer the control to pei core.
;
;------------------------------------------------------------------------------
#include <Base.h>
.686p
.xmm
.model small, c
EXTRN SecStartup:NEAR
; Pcds
EXTRN PcdGet32 (PcdPayloadFdMemBase):DWORD
.code
;
; SecCore Entry Point
;
; Processor is in flat protected mode
;
; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test)
; @param[in] DI 'BP': boot-strap processor, or 'AP': application processor
; @param[in] EBP Pointer to the start of the Boot Firmware Volume
;
; @return None This routine does not return
;
_ModuleEntryPoint PROC PUBLIC
;
; Disable all the interrupts
;
cli
;
; Construct the temporary memory at 0x80000, length 0x10000
;
mov esp, (BASE_512KB + SIZE_64KB)
;
; Pass BFV into the PEI Core
;
push PcdGet32 (PcdPayloadFdMemBase)
;
; Pass stack base into the PEI Core
;
push BASE_512KB
;
; Pass stack size into the PEI Core
;
push SIZE_64KB
;
; Pass Control into the PEI Core
;
call SecStartup
_ModuleEntryPoint ENDP
END

66
CorebootModulePkg/SecCore/Ia32/SecEntry.nasm
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@ -1,66 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Entry point for the coreboot UEFI payload.
;
;------------------------------------------------------------------------------
SECTION .text
; C Functions
extern ASM_PFX(SecStartup)
; Pcds
extern ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))
;
; SecCore Entry Point
;
; Processor is in flat protected mode
;
; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test)
; @param[in] DI 'BP': boot-strap processor, or 'AP': application processor
; @param[in] EBP Pointer to the start of the Boot Firmware Volume
;
; @return None This routine does not return
;
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
;
; Disable all the interrupts
;
cli
;
; Construct the temporary memory at 0x80000, length 0x10000
;
mov esp, (BASE_512KB + SIZE_64KB)
;
; Pass BFV into the PEI Core
;
push DWORD [ASM_PFX(PcdGet32 (PcdPayloadFdMemBase))]
;
; Pass stack base into the PEI Core
;
push BASE_512KB
;
; Pass stack size into the PEI Core
;
push SIZE_64KB
;
; Pass Control into the PEI Core
;
call ASM_PFX(SecStartup)
;
; Should never return
;
jmp $

76
CorebootModulePkg/SecCore/Ia32/Stack.asm
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@ -1,76 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Switch the stack from temporary memory to permanent memory.
;
;------------------------------------------------------------------------------
.586p
.model flat,C
.code
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; SecSwitchStack (
; UINT32 TemporaryMemoryBase,
; UINT32 PermenentMemoryBase
; );
;------------------------------------------------------------------------------
SecSwitchStack PROC
;
; Save three register: eax, ebx, ecx
;
push eax
push ebx
push ecx
push edx
;
; !!CAUTION!! this function address's is pushed into stack after
; migration of whole temporary memory, so need save it to permanent
; memory at first!
;
mov ebx, [esp + 20] ; Save the first parameter
mov ecx, [esp + 24] ; Save the second parameter
;
; Save this function's return address into permanent memory at first.
; Then, Fixup the esp point to permanent memory
;
mov eax, esp
sub eax, ebx
add eax, ecx
mov edx, dword ptr [esp] ; copy pushed register's value to permanent memory
mov dword ptr [eax], edx
mov edx, dword ptr [esp + 4]
mov dword ptr [eax + 4], edx
mov edx, dword ptr [esp + 8]
mov dword ptr [eax + 8], edx
mov edx, dword ptr [esp + 12]
mov dword ptr [eax + 12], edx
mov edx, dword ptr [esp + 16] ; Update this function's return address into permanent memory
mov dword ptr [eax + 16], edx
mov esp, eax ; From now, esp is pointed to permanent memory
;
; Fixup the ebp point to permanent memory
;
mov eax, ebp
sub eax, ebx
add eax, ecx
mov ebp, eax ; From now, ebp is pointed to permanent memory
pop edx
pop ecx
pop ebx
pop eax
ret
SecSwitchStack ENDP
END

72
CorebootModulePkg/SecCore/Ia32/Stack.nasm
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@ -1,72 +0,0 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
;
; Switch the stack from temporary memory to permanent memory.
;
;------------------------------------------------------------------------------
SECTION .text
;------------------------------------------------------------------------------
; VOID
; EFIAPI
; SecSwitchStack (
; UINT32 TemporaryMemoryBase,
; UINT32 PermenentMemoryBase
; );
;------------------------------------------------------------------------------
global ASM_PFX(SecSwitchStack)
ASM_PFX(SecSwitchStack):
;
; Save three register: eax, ebx, ecx
;
push eax
push ebx
push ecx
push edx
;
; !!CAUTION!! this function address's is pushed into stack after
; migration of whole temporary memory, so need save it to permanent
; memory at first!
;
mov ebx, [esp + 20] ; Save the first parameter
mov ecx, [esp + 24] ; Save the second parameter
;
; Save this function's return address into permanent memory at first.
; Then, Fixup the esp point to permanent memory
;
mov eax, esp
sub eax, ebx
add eax, ecx
mov edx, [esp] ; copy pushed register's value to permanent memory
mov [eax], edx
mov edx, [esp + 4]
mov [eax + 4], edx
mov edx, [esp + 8]
mov [eax + 8], edx
mov edx, [esp + 12]
mov [eax + 12], edx
mov edx, [esp + 16] ; Update return address into permanent memory
mov [eax + 16], edx
mov esp, eax ; From now, esp is pointed to permanent memory
;
; Fixup the ebp point to permanent memory
;
mov eax, ebp
sub eax, ebx
add eax, ecx
mov ebp, eax ; From now, ebp is pointed to permanent memory
pop edx
pop ecx
pop ebx
pop eax
ret

57
CorebootModulePkg/SecCore/SecCore.inf
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@ -1,57 +0,0 @@
## @file
# This is the first module taking control from the coreboot.
#
# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SecCore
FILE_GUID = BA7BE337-6CFB-4dbb-B26C-21EC2FC16073
MODULE_TYPE = SEC
VERSION_STRING = 1.0
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
SecMain.c
SecMain.h
FindPeiCore.c
[Sources.IA32]
Ia32/Stack.nasm
Ia32/SecEntry.nasm
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
CorebootModulePkg/CorebootModulePkg.dec
[LibraryClasses]
BaseMemoryLib
DebugLib
BaseLib
PcdLib
DebugAgentLib
UefiCpuLib
PeCoffGetEntryPointLib
PeCoffExtraActionLib
[Ppis]
gEfiSecPlatformInformationPpiGuid # PPI ALWAYS_PRODUCED
gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
[Pcd]
gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemBase
gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemSize

285
CorebootModulePkg/SecCore/SecMain.c
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@ -1,285 +0,0 @@
/** @file
C functions in SEC
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "SecMain.h"
EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {
SecTemporaryRamSupport
};
EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {
{
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiTemporaryRamSupportPpiGuid,
&gSecTemporaryRamSupportPpi
}
};
//
// These are IDT entries pointing to 10:FFFFFFE4h.
//
UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL;
/**
Caller provided function to be invoked at the end of InitializeDebugAgent().
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] Context The first input parameter of InitializeDebugAgent().
**/
VOID
EFIAPI
SecStartupPhase2(
IN VOID *Context
);
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param SizeOfRam Size of the temporary memory available for use.
@param TempRamBase Base address of temporary ram
@param BootFirmwareVolume Base address of the Boot Firmware Volume.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack;
UINT32 Index;
UINT32 PeiStackSize;
PeiStackSize = (SizeOfRam >> 1);
ASSERT (PeiStackSize < SizeOfRam);
//
// Process all libraries constructor function linked to SecCore.
//
ProcessLibraryConstructorList ();
//
// Initialize floating point operating environment
// to be compliant with UEFI spec.
//
InitializeFloatingPointUnits ();
// |-------------------|---->
// |Idt Table |
// |-------------------|
// |PeiService Pointer | PeiStackSize
// |-------------------|
// | |
// | Stack |
// |-------------------|---->
// | |
// | |
// | Heap | PeiTemporaryRamSize
// | |
// | |
// |-------------------|----> TempRamBase
IdtTableInStack.PeiService = 0;
for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {
CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));
}
IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;
IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);
AsmWriteIdtr (&IdtDescriptor);
//
// Update the base address and length of Pei temporary memory
//
SecCoreData.DataSize = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;
SecCoreData.BootFirmwareVolumeSize = (UINTN)(0x100000000ULL - (UINTN) BootFirmwareVolume);
SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;
SecCoreData.TemporaryRamSize = SizeOfRam;
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SizeOfRam - PeiStackSize;
SecCoreData.StackBase = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = PeiStackSize;
//
// Initialize Debug Agent to support source level debug in SEC/PEI phases before memory ready.
//
InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, &SecCoreData, SecStartupPhase2);
}
/**
Caller provided function to be invoked at the end of InitializeDebugAgent().
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] Context The first input parameter of InitializeDebugAgent().
**/
VOID
EFIAPI
SecStartupPhase2(
IN VOID *Context
)
{
EFI_SEC_PEI_HAND_OFF *SecCoreData;
EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
SecCoreData = (EFI_SEC_PEI_HAND_OFF *) Context;
//
// Find Pei Core entry point. It will report SEC and Pei Core debug information if remote debug
// is enabled.
//
FindAndReportEntryPoints ((EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase, &PeiCoreEntryPoint);
if (PeiCoreEntryPoint == NULL)
{
CpuDeadLoop ();
}
//
// Transfer the control to the PEI core
//
ASSERT (PeiCoreEntryPoint != NULL);
(*PeiCoreEntryPoint) (SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPeiSecPlatformInformationPpi);
//
// Should not come here.
//
return ;
}
/**
This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
permanent memory.
@param PeiServices Pointer to the PEI Services Table.
@param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
Temporary RAM contents.
@param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
Temporary RAM contents.
@param CopySize Amount of memory to migrate from temporary to permanent memory.
@retval EFI_SUCCESS The data was successfully returned.
@retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
TemporaryMemoryBase > PermanentMemoryBase.
**/
EFI_STATUS
EFIAPI
SecTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize
)
{
IA32_DESCRIPTOR IdtDescriptor;
VOID* OldHeap;
VOID* NewHeap;
VOID* OldStack;
VOID* NewStack;
DEBUG_AGENT_CONTEXT_POSTMEM_SEC DebugAgentContext;
BOOLEAN OldStatus;
UINTN PeiStackSize;
PeiStackSize = (CopySize >> 1);
ASSERT (PeiStackSize < CopySize);
//
// |-------------------|---->
// | Stack | PeiStackSize
// |-------------------|---->
// | Heap | PeiTemporaryRamSize
// |-------------------|----> TempRamBase
//
// |-------------------|---->
// | Heap | PeiTemporaryRamSize
// |-------------------|---->
// | Stack | PeiStackSize
// |-------------------|----> PermanentMemoryBase
//
OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
NewHeap = (VOID*)((UINTN)PermanentMemoryBase + PeiStackSize);
OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize - PeiStackSize);
NewStack = (VOID*)(UINTN)PermanentMemoryBase;
DebugAgentContext.HeapMigrateOffset = (UINTN)NewHeap - (UINTN)OldHeap;
DebugAgentContext.StackMigrateOffset = (UINTN)NewStack - (UINTN)OldStack;
OldStatus = SaveAndSetDebugTimerInterrupt (FALSE);
//
// Initialize Debug Agent to support source level debug in PEI phase after memory ready.
// It will build HOB and fix up the pointer in IDT table.
//
InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, (VOID *) &DebugAgentContext, NULL);
//
// Migrate Heap
//
CopyMem (NewHeap, OldHeap, CopySize - PeiStackSize);
//
// Migrate Stack
//
CopyMem (NewStack, OldStack, PeiStackSize);
//
// We need *not* fix the return address because currently,
// The PeiCore is executed in flash.
//
//
// Rebase IDT table in permanent memory
//
AsmReadIdtr (&IdtDescriptor);
IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack + (UINTN)NewStack;
AsmWriteIdtr (&IdtDescriptor);
//
// Program MTRR
//
//
// SecSwitchStack function must be invoked after the memory migration
// immediately, also we need fixup the stack change caused by new call into
// permanent memory.
//
SecSwitchStack (
(UINT32) (UINTN) OldStack,
(UINT32) (UINTN) NewStack
);
SaveAndSetDebugTimerInterrupt (OldStatus);
return EFI_SUCCESS;
}

128
CorebootModulePkg/SecCore/SecMain.h
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@ -1,128 +0,0 @@
/** @file
Master header file for SecCore.
Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _SEC_CORE_H_
#define _SEC_CORE_H_
#include <PiPei.h>
#include <Ppi/SecPlatformInformation.h>
#include <Ppi/TemporaryRamSupport.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiCpuLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <Library/PeCoffExtraActionLib.h>
#include <Library/DebugAgentLib.h>
#define SEC_IDT_ENTRY_COUNT 34
typedef struct _SEC_IDT_TABLE {
//
// Reserved 8 bytes preceding IDT to store EFI_PEI_SERVICES**, since IDT base
// address should be 8-byte alignment.
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to store
// EFI_PEI_SERVICES**
//
UINT64 PeiService;
UINT64 IdtTable[SEC_IDT_ENTRY_COUNT];
} SEC_IDT_TABLE;
/**
Switch the stack in the temporary memory to the one in the permanent memory.
This function must be invoked after the memory migration immediately. The relative
position of the stack in the temporary and permanent memory is same.
@param TemporaryMemoryBase Base address of the temporary memory.
@param PermenentMemoryBase Base address of the permanent memory.
**/
VOID
EFIAPI
SecSwitchStack (
UINT32 TemporaryMemoryBase,
UINT32 PermenentMemoryBase
);
/**
This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into
permanent memory.
@param PeiServices Pointer to the PEI Services Table.
@param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the
Temporary RAM contents.
@param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the
Temporary RAM contents.
@param CopySize Amount of memory to migrate from temporary to permanent memory.
@retval EFI_SUCCESS The data was successfully returned.
@retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when
TemporaryMemoryBase > PermanentMemoryBase.
**/
EFI_STATUS
EFIAPI
SecTemporaryRamSupport (
IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
IN UINTN CopySize
);
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param SizeOfRam Size of the temporary memory available for use.
@param TempRamBase Base address of temporary ram
@param BootFirmwareVolume Base address of the Boot Firmware Volume.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume
);
/**
Find and return Pei Core entry point.
It also find SEC and PEI Core file debug information. It will report them if
remote debug is enabled.
@param BootFirmwareVolumePtr Point to the boot firmware volume.
@param PeiCoreEntryPoint Point to the PEI core entry point.
**/
VOID
EFIAPI
FindAndReportEntryPoints (
IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr,
OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
);
/**
Autogenerated function that calls the library constructors for all of the module's
dependent libraries. This function must be called by the SEC Core once a stack has
been established.
**/
VOID
EFIAPI
ProcessLibraryConstructorList (
VOID
);
#endif

82
CorebootPayloadPkg/BuildAndIntegrationInstructions.txt
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@ -1,82 +0,0 @@
================================================================================
Build And Integration Instructions
2014 June 24th
================================================================================
================================================================================
DISCLAIMER
================================================================================
This release note as well as the software described in it is furnished under license
and may only be used or copied in accordance with the terms of the license. The
information in this manual is furnished for informational use only, is subject to
change without notice, and should not be construed as a commitment by Intel Corporation.
Intel Corporation assumes no responsibility or liability for any errors or inaccuracies
that may appear in this document or any software that may be provided in association
with this document.
Except as permitted by such license, no part of this document may be reproduced,
stored in a retrieval system, or transmitted in any form or by any means without
the express written consent of Intel Corporation.
================================================================================
INDEX
================================================================================
A. INTRODUCTION
B. HOW TO BUILD
C. HOW TO INTEGRATE
================================================================================
A. INTRODUCTION
================================================================================
This document provides instructions on how to build Coreboot Uefi Payload and
how to integrate it into coreboot firmware.
================================================================================
B. HOW TO BUILD
================================================================================
1. Run the below two commands in windows command prompt window:
edksetup.bat
For debug ia32 build:
build -a IA32 -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -b DEBUG -t <ToolChain>
For release ia32 build:
build -a IA32 -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -b RELEASE -t <ToolChain>
For debug X64 build:
build -a IA32 -a X64 -p CorebootPayloadPkg\CorebootPayloadPkgIa32X64.dsc -b DEBUG -t <ToolChain>
For release X64 build:
build -a IA32 -a X64 -p CorebootPayloadPkg\CorebootPayloadPkgIa32X64.dsc -b RELEASE -t <ToolChain>
<ToolChain> is the EDK II build environment on your host. Currently it was tested with VS2008x64 toolchain.
For details about EDK II build steps, refer to http://svn.code.sf.net/p/edk2/code/branches/UDK2014/BuildNotes2.txt
2. If build is successfully, the payload image (UEFIPAYLOAD.fd) will be generated inside the folder of Build\CorebootPayloadPkg.
================================================================================
C. HOW TO INTEGRATE
================================================================================
1. Copy the payload image (UEFIPAYLOAD.fd) into the top-level directory of Coreboot source tree.
2. Run "make menuconfig" in linux console to start Coreboot configuration surface.
3. In the Payload section,
1) Choose "An ELF executable payload" for the option of "Add a payload".
2) Type the path of payload image for the option of "Payload path and filename".
3) Select the option of "Use LZMA compression for payloads".
4. If the graphics console is required in Coreboot UEFI payload, running VGA option rom should be enabled.
For details:
1) In the Device section, select the option of "Run VGA Option ROMs".
2) In the VGA BIOS section, select the option of "Add a VGA BIOS Image", Input the path of vga bios image
for the option of VGA BIOS path and filename, give the values of vendor id and device id for the option
of "VGA device PCI IDs".
3) In the Display section,
Select the option of "Set framebuffer graphics resolution"
Choose a right display mode for the option of "framebuffer graphics resolution".
Note: If the boot OS is windows, please choose the display mode supporting 32 bit color.
Select the option of "Keep VESA framebuffer"
5. Press ESC key to exit the Coreboot configuration surface. If there is a question prompted like "Do you wish to save your new configuration?",
choose Yes.
6. Run "make" to build the coreboot firmware image.

48
CorebootPayloadPkg/CorebootPayloadPkg.dec
View File

@ -1,48 +0,0 @@
## @file
# Coreboot Payload Package
#
# Provides drivers and definitions to create uefi payload for coreboot.
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
DEC_SPECIFICATION = 0x00010005
PACKAGE_NAME = CorebootPayloadPkg
PACKAGE_GUID = 58ABC905-951E-472e-8590-77BA8A50BE63
PACKAGE_VERSION = 0.1
[LibraryClasses]
[Guids]
#
## Defines the token space for the Coreboot Payload Package PCDs.
#
gUEfiCorebootPayloadPkgTokenSpaceGuid = {0x1d127ea, 0xf6f1, 0x4ef6, {0x94, 0x15, 0x8a, 0x0, 0x0, 0x93, 0xf8, 0x9d}}
#
# Gop Temp
#
gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }
[Ppis]
[Protocols]
#
# Gop Temp
#
gPlatformGOPPolicyGuid = { 0xec2e931b, 0x3281, 0x48a5, { 0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d } }
################################################################################
#
# PCD Declarations section - list of all PCDs Declared by this Package
# Only this package should be providing the
# declaration, other packages should not.
#
################################################################################
[PcdsFixedAtBuild, PcdsPatchableInModule]
[PcdsDynamic, PcdsDynamicEx]

285
CorebootPayloadPkg/CorebootPayloadPkg.fdf
View File

@ -1,285 +0,0 @@
## @file
# Coreboot Payload Package
#
# Provides drivers and definitions to create uefi payload for coreboot.
#
# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
################################################################################
[FD.UefiPayload]
BaseAddress = 0x800000|gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemBase
Size = 0x410000|gUefiCorebootModulePkgTokenSpaceGuid.PcdPayloadFdMemSize
ErasePolarity = 1
BlockSize = 0x1000
NumBlocks = 0x410
0x00000000|0x030000
FV = PEIFV
0x00030000|0x3E0000
FV = DXEFV
################################################################################
[FV.PEIFV]
BlockSize = 0x1000
FvAlignment = 16
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
INF CorebootModulePkg/SecCore/SecCore.inf
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
INF CorebootModulePkg/CbSupportPei/CbSupportPei.inf
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
################################################################################
[FV.DXEFV]
BlockSize = 0x1000
FvForceRebase = FALSE
FvAlignment = 16
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
APRIORI DXE {
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
}
#
# DXE Phase modules
#
INF MdeModulePkg/Core/Dxe/DxeMain.inf
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
INF UefiCpuPkg/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
!if $(USE_HPET_TIMER) == TRUE
INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
!else
INF PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
!endif
INF MdeModulePkg/Universal/Metronome/Metronome.inf
INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# PCI Support
#
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
#
# ISA Support
#
INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
#
# Console Support
#
INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
#
# SCSI/ATA/IDE/DISK Support
#
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
INF CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
INF FatPkg/EnhancedFatDxe/Fat.inf
#
# SD/eMMC Support
#
INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf
INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
#
# Usb Support
#
INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# OHCI Support
#
INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf
#
# Shell
#
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
INF ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf
INF ShellPkg/Application/Shell/Shell.inf
FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
SECTION RAW = MdeModulePkg/Logo/Logo.bmp
}
#
# Framebuffer Gop
#
INF CorebootPayloadPkg/FbGop/FbGop.inf
################################################################################
#
# Rules are use with the [FV] section's module INF type to define
# how an FFS file is created for a given INF file. The following Rule are the default
# rules for the different module type. User can add the customized rules to define the
# content of the FFS file.
#
################################################################################
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) {
PE32 PE32 Align=32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
PE32 PE32 Align=Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 Align=Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.DXE_RUNTIME_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_DRIVER.BINARY]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_APPLICATION.BINARY]
FILE APPLICATION = $(NAMED_GUID) {
PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.USER_DEFINED.ACPITABLE]
FILE FREEFORM = $(NAMED_GUID) {
RAW ACPI |.acpi
RAW ASL |.aml
}
[Rule.Common.USER_DEFINED.CSM]
FILE FREEFORM = $(NAMED_GUID) {
RAW BIN |.bin
}
[Rule.Common.SEC.RESET_VECTOR]
FILE RAW = $(NAMED_GUID) {
RAW RAW |.raw
}

574
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
View File

@ -1,574 +0,0 @@
## @file
# Coreboot Payload Package
#
# Provides drivers and definitions to create uefi payload for coreboot.
#
# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = CorebootPayloadPkg
PLATFORM_GUID = F71608AB-D63D-4491-B744-A99998C8CD96
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
SUPPORTED_ARCHITECTURES = IA32
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
OUTPUT_DIRECTORY = Build/CorebootPayloadPkgIA32
FLASH_DEFINITION = CorebootPayloadPkg/CorebootPayloadPkg.fdf
DEFINE SECURE_BOOT_ENABLE = FALSE
DEFINE SOURCE_DEBUG_ENABLE = FALSE
#
# CPU options
#
DEFINE MAX_LOGICAL_PROCESSORS = 64
#
# PCI options
#
DEFINE PCIE_BASE = 0xE0000000
#
# Serial port set up
#
DEFINE BAUD_RATE = 115200
DEFINE SERIAL_CLOCK_RATE = 1843200
DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity
DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE
DEFINE SERIAL_DETECT_CABLE = FALSE
DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO
DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16
DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE)
DEFINE UART_DEFAULT_DATA_BITS = 8
DEFINE UART_DEFAULT_PARITY = 1
DEFINE UART_DEFAULT_STOP_BITS = 1
DEFINE DEFAULT_TERMINAL_TYPE = 0
#
# typedef struct {
# UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
# UINT16 DeviceId; ///< Device ID to match the PCI device
# UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
# UINT64 Offset; ///< The byte offset into to the BAR
# UINT8 BarIndex; ///< Which BAR to get the UART base address
# UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
# UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
# UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
# UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
# Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000)
#
# [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]
DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}
#
# Chipset options
#
DEFINE USE_HPET_TIMER = FALSE
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
################################################################################
#
# SKU Identification section - list of all SKU IDs supported by this Platform.
#
################################################################################
[SkuIds]
0|DEFAULT
################################################################################
#
# Library Class section - list of all Library Classes needed by this Platform.
#
################################################################################
[LibraryClasses]
#
# Entry point
#
PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
#
# Basic
#
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
!if $(PCIE_BASE) == 0
PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
!else
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
!endif
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
#
# UEFI & PI
#
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
#
# Generic Modules
#
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
#
# CPU
#
MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
#
# Platform
#
TimerLib|CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
CbPlatformSupportLib|CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.inf
#
# Misc
#
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
!if $(SOURCE_DEBUG_ENABLE) == TRUE
PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
!else
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
!endif
CbParseLib|CorebootModulePkg/Library/CbParseLib/CbParseLib.inf
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
[LibraryClasses.IA32.SEC]
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
[LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
!if $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
!endif
[LibraryClasses.common.DXE_CORE]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
!if $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
[LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
!if $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
#
################################################################################
[PcdsFeatureFlag]
!if $(TARGET) == DEBUG
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
!else
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
!endif
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
[PcdsFixedAtBuild]
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000
#
# Make VariableRuntimeDxe work at emulated non-volatile variable mode.
#
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)
!if $(SOURCE_DEBUG_ENABLE)
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
!endif
[PcdsPatchableInModule.common]
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
!if $(SOURCE_DEBUG_ENABLE)
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
!else
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
!endif
#
# The following parameters are set by Library/PlatformHookLib
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
#
# Enable these parameters to be set on the command line
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONTROL)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIAL_HARDWARE_FLOW_CONTROL)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CABLE)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)
#
# Set the proper Shell file GUID
#
# 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1c, 0x4f, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
################################################################################
#
# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsDynamicDefault]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
## This PCD defines the video horizontal resolution.
# This PCD could be set to 0 then video resolution could be at highest resolution.
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
## This PCD defines the video vertical resolution.
# This PCD could be set to 0 then video resolution could be at highest resolution.
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
## The PCD is used to specify the video horizontal resolution of text setup.
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0
## The PCD is used to specify the video vertical resolution of text setup.
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.
#
################################################################################
[Components.IA32]
#
# SEC Core
#
CorebootModulePkg/SecCore/SecCore.inf
#
# PEI Core
#
MdeModulePkg/Core/Pei/PeiMain.inf
#
# PEIM
#
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
CorebootModulePkg/CbSupportPei/CbSupportPei.inf
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
[Components.IA32]
#
# DXE Core
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
}
#
# Components that produce the architectural protocols
#
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
MdeModulePkg/Application/UiApp/UiApp.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
}
!if $(USE_HPET_TIMER) == TRUE
PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
!else
PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
!endif
MdeModulePkg/Universal/Metronome/Metronome.inf
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
#
# Following are the DXE drivers
#
MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
#
# SMBIOS Support
#
MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# ACPI Support
#
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
#
# PCI Support
#
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
}
#
# SCSI/ATA/IDE/DISK Support
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
FatPkg/EnhancedFatDxe/Fat.inf
CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf
MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
#
# SD/eMMC Support
#
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf
MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
#
# Usb Support
#
MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# OHCI support
#
QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf
#
# ISA Support
#
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
#
# Console Support
#
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
#
# Framebuffer Gop
#
CorebootPayloadPkg/FbGop/FbGop.inf
#------------------------------
# Build the shell
#------------------------------
#
# Shell Lib
#
[LibraryClasses]
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
[Components.IA32]
ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {
<PcdsFixedAtBuild>
## This flag is used to control initialization of the shell library
# This should be FALSE for compiling the dynamic command.
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf {
<PcdsFixedAtBuild>
## This flag is used to control initialization of the shell library
# This should be FALSE for compiling the dynamic command.
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
ShellPkg/Application/Shell/Shell.inf {
<PcdsFixedAtBuild>
## This flag is used to control initialization of the shell library
# This should be FALSE for compiling the shell application itself only.
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
#------------------------------
# Basic commands
#------------------------------
<LibraryClasses>
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
#------------------------------
# Networking commands
#------------------------------
<LibraryClasses>
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
#------------------------------
# Support libraries
#------------------------------
<LibraryClasses>
DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
}

575
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
View File

@ -1,575 +0,0 @@
## @file
# Coreboot Payload Package
#
# Provides drivers and definitions to create uefi payload for coreboot.
#
# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
PLATFORM_NAME = CorebootPayloadPkg
PLATFORM_GUID = F71608AB-D63D-4491-B744-A99998C8CD96
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
SUPPORTED_ARCHITECTURES = IA32|X64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
OUTPUT_DIRECTORY = Build/CorebootPayloadPkgX64
FLASH_DEFINITION = CorebootPayloadPkg/CorebootPayloadPkg.fdf
DEFINE SECURE_BOOT_ENABLE = FALSE
DEFINE SOURCE_DEBUG_ENABLE = FALSE
#
# CPU options
#
DEFINE MAX_LOGICAL_PROCESSORS = 64
#
# PCI options
#
DEFINE PCIE_BASE = 0xE0000000
#
# Serial port set up
#
DEFINE BAUD_RATE = 115200
DEFINE SERIAL_CLOCK_RATE = 1843200
DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity
DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE
DEFINE SERIAL_DETECT_CABLE = FALSE
DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO
DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16
DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE)
DEFINE UART_DEFAULT_DATA_BITS = 8
DEFINE UART_DEFAULT_PARITY = 1
DEFINE UART_DEFAULT_STOP_BITS = 1
DEFINE DEFAULT_TERMINAL_TYPE = 0
#
# typedef struct {
# UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
# UINT16 DeviceId; ///< Device ID to match the PCI device
# UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
# UINT64 Offset; ///< The byte offset into to the BAR
# UINT8 BarIndex; ///< Which BAR to get the UART base address
# UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
# UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
# UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
# UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
# Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1, Clock 1843200 (0x1c2000)
#
# [Vendor] [Device] [----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]
DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00, 0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}
#
# Chipset options
#
DEFINE USE_HPET_TIMER = FALSE
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
################################################################################
#
# SKU Identification section - list of all SKU IDs supported by this Platform.
#
################################################################################
[SkuIds]
0|DEFAULT
################################################################################
#
# Library Class section - list of all Library Classes needed by this Platform.
#
################################################################################
[LibraryClasses]
#
# Entry point
#
PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
#
# Basic
#
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
!if $(PCIE_BASE) == 0
PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
!else
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
!endif
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
#
# UEFI & PI
#
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
#
# Generic Modules
#
UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
#
# CPU
#
MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
#
# Platform
#
TimerLib|CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
CbPlatformSupportLib|CorebootModulePkg/Library/CbPlatformSupportLibNull/CbPlatformSupportLibNull.inf
#
# Misc
#
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
!if $(SOURCE_DEBUG_ENABLE) == TRUE
PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
!else
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
!endif
CbParseLib|CorebootModulePkg/Library/CbParseLib/CbParseLib.inf
DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
[LibraryClasses.IA32.SEC]
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
[LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.PEIM]
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
!if $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
!endif
[LibraryClasses.common.DXE_CORE]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
!if $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
[LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
!if $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
[LibraryClasses.common.DXE_RUNTIME_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
#
################################################################################
[PcdsFeatureFlag]
!if $(TARGET) == DEBUG
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
!else
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
!endif
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
[PcdsFixedAtBuild]
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000
#
# Make VariableRuntimeDxe work at emulated non-volatile variable mode.
#
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)
!if $(SOURCE_DEBUG_ENABLE)
gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
!endif
[PcdsPatchableInModule.common]
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
!if $(SOURCE_DEBUG_ENABLE)
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
!else
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
!endif
#
# The following parameters are set by Library/PlatformHookLib
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
#
# Enable these parameters to be set on the command line
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONTROL)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIAL_HARDWARE_FLOW_CONTROL)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CABLE)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)
#
# Set the proper Shell file GUID
#
# 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1c, 0x4f, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
################################################################################
#
# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
[PcdsDynamicDefault]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
## This PCD defines the video horizontal resolution.
# This PCD could be set to 0 then video resolution could be at highest resolution.
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
## This PCD defines the video vertical resolution.
# This PCD could be set to 0 then video resolution could be at highest resolution.
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
## The PCD is used to specify the video horizontal resolution of text setup.
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0
## The PCD is used to specify the video vertical resolution of text setup.
gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform.
#
################################################################################
[Components.IA32]
#
# SEC Core
#
CorebootModulePkg/SecCore/SecCore.inf
#
# PEI Core
#
MdeModulePkg/Core/Pei/PeiMain.inf
#
# PEIM
#
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
CorebootModulePkg/CbSupportPei/CbSupportPei.inf
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
[Components.X64]
#
# DXE Core
#
MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
}
#
# Components that produce the architectural protocols
#
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
UefiCpuPkg/CpuDxe/CpuDxe.inf
MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
MdeModulePkg/Application/UiApp/UiApp.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
}
!if $(USE_HPET_TIMER) == TRUE
PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
!else
PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
!endif
MdeModulePkg/Universal/Metronome/Metronome.inf
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
#
# Following are the DXE drivers
#
MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
}
MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
#
# SMBIOS Support
#
MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# ACPI Support
#
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
#
# PCI Support
#
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
<LibraryClasses>
PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
}
#
# SCSI/ATA/IDE/DISK Support
#
MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
FatPkg/EnhancedFatDxe/Fat.inf
CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf
MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
#
# SD/eMMC Support
#
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf
MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
#
# Usb Support
#
MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# OHCI support
#
QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf
#
# ISA Support
#
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
#
# Console Support
#
MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
#
# Framebuffer Gop
#
CorebootPayloadPkg/FbGop/FbGop.inf
#------------------------------
# Build the shell
#------------------------------
#
# Shell Lib
#
[LibraryClasses]
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
[Components.X64]
ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {
<PcdsFixedAtBuild>
## This flag is used to control initialization of the shell library
# This should be FALSE for compiling the dynamic command.
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
ShellPkg/DynamicCommand/DpDynamicCommand/DpDynamicCommand.inf {
<PcdsFixedAtBuild>
## This flag is used to control initialization of the shell library
# This should be FALSE for compiling the dynamic command.
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
}
ShellPkg/Application/Shell/Shell.inf {
<PcdsFixedAtBuild>
## This flag is used to control initialization of the shell library
# This should be FALSE for compiling the shell application itself only.
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
#------------------------------
# Basic commands
#------------------------------
<LibraryClasses>
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
#------------------------------
# Networking commands
#------------------------------
<LibraryClasses>
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
#------------------------------
# Support libraries
#------------------------------
<LibraryClasses>
DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
}

306
CorebootPayloadPkg/FbGop/ComponentName.c
View File

@ -1,306 +0,0 @@
/** @file
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "FbGop.h"
//
// EFI Component Name Functions
//
/**
Retrieves a Unicode string that is the user readable name of the driver.
This function retrieves the user readable name of a driver in the form of a
Unicode string. If the driver specified by This has a user readable name in
the language specified by Language, then a pointer to the driver name is
returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
by This does not support the language specified by Language,
then EFI_UNSUPPORTED is returned.
@param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
EFI_COMPONENT_NAME_PROTOCOL instance.
@param Language[in] A pointer to a Null-terminated ASCII string
array indicating the language. This is the
language of the driver name that the caller is
requesting, and it must match one of the
languages specified in SupportedLanguages. The
number of languages supported by a driver is up
to the driver writer. Language is specified
in RFC 4646 or ISO 639-2 language code format.
@param DriverName[out] A pointer to the Unicode string to return.
This Unicode string is the name of the
driver specified by This in the language
specified by Language.
@retval EFI_SUCCESS The Unicode string for the Driver specified by
This and the language specified by Language was
returned in DriverName.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER DriverName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This does not support
the language specified by Language.
**/
EFI_STATUS
EFIAPI
FbGopComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
);
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
This function retrieves the user readable name of the controller specified by
ControllerHandle and ChildHandle in the form of a Unicode string. If the
driver specified by This has a user readable name in the language specified by
Language, then a pointer to the controller name is returned in ControllerName,
and EFI_SUCCESS is returned. If the driver specified by This is not currently
managing the controller specified by ControllerHandle and ChildHandle,
then EFI_UNSUPPORTED is returned. If the driver specified by This does not
support the language specified by Language, then EFI_UNSUPPORTED is returned.
@param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
EFI_COMPONENT_NAME_PROTOCOL instance.
@param ControllerHandle[in] The handle of a controller that the driver
specified by This is managing. This handle
specifies the controller whose name is to be
returned.
@param ChildHandle[in] The handle of the child controller to retrieve
the name of. This is an optional parameter that
may be NULL. It will be NULL for device
drivers. It will also be NULL for a bus drivers
that wish to retrieve the name of the bus
controller. It will not be NULL for a bus
driver that wishes to retrieve the name of a
child controller.
@param Language[in] A pointer to a Null-terminated ASCII string
array indicating the language. This is the
language of the driver name that the caller is
requesting, and it must match one of the
languages specified in SupportedLanguages. The
number of languages supported by a driver is up
to the driver writer. Language is specified in
RFC 4646 or ISO 639-2 language code format.
@param ControllerName[out] A pointer to the Unicode string to return.
This Unicode string is the name of the
controller specified by ControllerHandle and
ChildHandle in the language specified by
Language from the point of view of the driver
specified by This.
@retval EFI_SUCCESS The Unicode string for the user readable name in
the language specified by Language for the
driver specified by This was returned in
DriverName.
@retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
@retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
EFI_HANDLE.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER ControllerName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This is not currently
managing the controller specified by
ControllerHandle and ChildHandle.
@retval EFI_UNSUPPORTED The driver specified by This does not support
the language specified by Language.
**/
EFI_STATUS
EFIAPI
FbGopComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
);
//
// EFI Component Name Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gFbGopComponentName = {
FbGopComponentNameGetDriverName,
FbGopComponentNameGetControllerName,
"eng"
};
//
// EFI Component Name 2 Protocol
//
GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gFbGopComponentName2 = {
(EFI_COMPONENT_NAME2_GET_DRIVER_NAME) FbGopComponentNameGetDriverName,
(EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) FbGopComponentNameGetControllerName,
"en"
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mFbGopDriverNameTable[] = {
{
"eng;en",
L"FB GOP Video Driver"
},
{
NULL,
NULL
}
};
/**
Retrieves a Unicode string that is the user readable name of the driver.
This function retrieves the user readable name of a driver in the form of a
Unicode string. If the driver specified by This has a user readable name in
the language specified by Language, then a pointer to the driver name is
returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
by This does not support the language specified by Language,
then EFI_UNSUPPORTED is returned.
@param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
EFI_COMPONENT_NAME_PROTOCOL instance.
@param Language[in] A pointer to a Null-terminated ASCII string
array indicating the language. This is the
language of the driver name that the caller is
requesting, and it must match one of the
languages specified in SupportedLanguages. The
number of languages supported by a driver is up
to the driver writer. Language is specified
in RFC 4646 or ISO 639-2 language code format.
@param DriverName[out] A pointer to the Unicode string to return.
This Unicode string is the name of the
driver specified by This in the language
specified by Language.
@retval EFI_SUCCESS The Unicode string for the Driver specified by
This and the language specified by Language was
returned in DriverName.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER DriverName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This does not support
the language specified by Language.
**/
EFI_STATUS
EFIAPI
FbGopComponentNameGetDriverName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN CHAR8 *Language,
OUT CHAR16 **DriverName
)
{
return LookupUnicodeString2 (
Language,
This->SupportedLanguages,
mFbGopDriverNameTable,
DriverName,
(BOOLEAN)(This == &gFbGopComponentName)
);
}
/**
Retrieves a Unicode string that is the user readable name of the controller
that is being managed by a driver.
This function retrieves the user readable name of the controller specified by
ControllerHandle and ChildHandle in the form of a Unicode string. If the
driver specified by This has a user readable name in the language specified by
Language, then a pointer to the controller name is returned in ControllerName,
and EFI_SUCCESS is returned. If the driver specified by This is not currently
managing the controller specified by ControllerHandle and ChildHandle,
then EFI_UNSUPPORTED is returned. If the driver specified by This does not
support the language specified by Language, then EFI_UNSUPPORTED is returned.
@param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
EFI_COMPONENT_NAME_PROTOCOL instance.
@param ControllerHandle[in] The handle of a controller that the driver
specified by This is managing. This handle
specifies the controller whose name is to be
returned.
@param ChildHandle[in] The handle of the child controller to retrieve
the name of. This is an optional parameter that
may be NULL. It will be NULL for device
drivers. It will also be NULL for a bus drivers
that wish to retrieve the name of the bus
controller. It will not be NULL for a bus
driver that wishes to retrieve the name of a
child controller.
@param Language[in] A pointer to a Null-terminated ASCII string
array indicating the language. This is the
language of the driver name that the caller is
requesting, and it must match one of the
languages specified in SupportedLanguages. The
number of languages supported by a driver is up
to the driver writer. Language is specified in
RFC 4646 or ISO 639-2 language code format.
@param ControllerName[out] A pointer to the Unicode string to return.
This Unicode string is the name of the
controller specified by ControllerHandle and
ChildHandle in the language specified by
Language from the point of view of the driver
specified by This.
@retval EFI_SUCCESS The Unicode string for the user readable name in
the language specified by Language for the
driver specified by This was returned in
DriverName.
@retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
@retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
EFI_HANDLE.
@retval EFI_INVALID_PARAMETER Language is NULL.
@retval EFI_INVALID_PARAMETER ControllerName is NULL.
@retval EFI_UNSUPPORTED The driver specified by This is not currently
managing the controller specified by
ControllerHandle and ChildHandle.
@retval EFI_UNSUPPORTED The driver specified by This does not support
the language specified by Language.
**/
EFI_STATUS
EFIAPI
FbGopComponentNameGetControllerName (
IN EFI_COMPONENT_NAME_PROTOCOL *This,
IN EFI_HANDLE ControllerHandle,
IN EFI_HANDLE ChildHandle OPTIONAL,
IN CHAR8 *Language,
OUT CHAR16 **ControllerName
)
{
return EFI_UNSUPPORTED;
}

1536
CorebootPayloadPkg/FbGop/FbGop.c
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413
CorebootPayloadPkg/FbGop/FbGop.h
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/** @file
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FB_GOP_H_
#define _FB_GOP_H_
#include <Protocol/PciIo.h>
#include <Protocol/DevicePath.h>
#include <Protocol/GraphicsOutput.h>
#include <Protocol/EdidActive.h>
#include <Protocol/EdidDiscovered.h>
#include <Guid/StatusCodeDataTypeId.h>
#include <Guid/EventGroup.h>
#include <Guid/FrameBufferInfoGuid.h>
#include <Library/PcdLib.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <IndustryStandard/Pci.h>
//
// Packed format support: The number of bits reserved for each of the colors and the actual
// position of RGB in the frame buffer is specified in the VBE Mode information
//
typedef struct {
UINT8 Position; // Position of the color
UINT8 Mask; // The number of bits expressed as a mask
} FB_VIDEO_COLOR_PLACEMENT;
//
// BIOS Graphics Output Graphical Mode Data
//
typedef struct {
UINT16 VbeModeNumber;
UINT16 BytesPerScanLine;
VOID *LinearFrameBuffer;
UINTN FrameBufferSize;
UINT32 HorizontalResolution;
UINT32 VerticalResolution;
UINT32 ColorDepth;
UINT32 RefreshRate;
UINT32 BitsPerPixel;
FB_VIDEO_COLOR_PLACEMENT Red;
FB_VIDEO_COLOR_PLACEMENT Green;
FB_VIDEO_COLOR_PLACEMENT Blue;
FB_VIDEO_COLOR_PLACEMENT Reserved;
EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;
EFI_PIXEL_BITMASK PixelBitMask;
} FB_VIDEO_MODE_DATA;
//
// BIOS video child handle private data Structure
//
#define FB_VIDEO_DEV_SIGNATURE SIGNATURE_32 ('B', 'V', 'M', 'p')
typedef struct {
UINTN Signature;
EFI_HANDLE Handle;
//
// Consumed Protocols
//
EFI_PCI_IO_PROTOCOL *PciIo;
//
// Produced Protocols
//
EFI_GRAPHICS_OUTPUT_PROTOCOL GraphicsOutput;
EFI_EDID_DISCOVERED_PROTOCOL EdidDiscovered;
EFI_EDID_ACTIVE_PROTOCOL EdidActive;
//
// Graphics Output Protocol related fields
//
UINTN CurrentMode;
UINTN MaxMode;
FB_VIDEO_MODE_DATA *ModeData;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL *VbeFrameBuffer;
//
// Status code
//
EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;
} FB_VIDEO_DEV;
#define FB_VIDEO_DEV_FROM_PCI_IO_THIS(a) CR (a, FB_VIDEO_DEV, PciIo, FB_VIDEO_DEV_SIGNATURE)
#define FB_VIDEO_DEV_FROM_GRAPHICS_OUTPUT_THIS(a) CR (a, FB_VIDEO_DEV, GraphicsOutput, FB_VIDEO_DEV_SIGNATURE)
#define GRAPHICS_OUTPUT_INVALIDE_MODE_NUMBER 0xffff
//
// Global Variables
//
extern EFI_DRIVER_BINDING_PROTOCOL gFbGopDriverBinding;
extern EFI_COMPONENT_NAME_PROTOCOL gFbGopComponentName;
extern EFI_COMPONENT_NAME2_PROTOCOL gFbGopComponentName2;
//
// Driver Binding Protocol functions
//
/**
Supported.
@param This Pointer to driver binding protocol
@param Controller Controller handle to connect
@param RemainingDevicePath A pointer to the remaining portion of a device
path
@retval EFI_STATUS EFI_SUCCESS:This controller can be managed by this
driver, Otherwise, this controller cannot be
managed by this driver
**/
EFI_STATUS
EFIAPI
FbGopDriverBindingSupported (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
Install Graphics Output Protocol onto VGA device handles.
@param This Pointer to driver binding protocol
@param Controller Controller handle to connect
@param RemainingDevicePath A pointer to the remaining portion of a device
path
@return EFI_STATUS
**/
EFI_STATUS
EFIAPI
FbGopDriverBindingStart (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
Stop.
@param This Pointer to driver binding protocol
@param Controller Controller handle to connect
@param NumberOfChildren Number of children handle created by this driver
@param ChildHandleBuffer Buffer containing child handle created
@retval EFI_SUCCESS Driver disconnected successfully from controller
@retval EFI_UNSUPPORTED Cannot find FB_VIDEO_DEV structure
**/
EFI_STATUS
EFIAPI
FbGopDriverBindingStop (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE Controller,
IN UINTN NumberOfChildren,
IN EFI_HANDLE *ChildHandleBuffer
);
//
// Private worker functions
//
/**
Check for VBE device.
@param FbGopPrivate Pointer to FB_VIDEO_DEV structure
@retval EFI_SUCCESS VBE device found
**/
EFI_STATUS
FbGopCheckForVbe (
IN OUT FB_VIDEO_DEV *FbGopPrivate
);
/**
Release resource for bios video instance.
@param FbGopPrivate Video child device private data structure
**/
VOID
FbGopDeviceReleaseResource (
FB_VIDEO_DEV *FbGopPrivate
);
//
// BIOS Graphics Output Protocol functions
//
/**
Graphics Output protocol interface to get video mode.
@param This Protocol instance pointer.
@param ModeNumber The mode number to return information on.
@param SizeOfInfo A pointer to the size, in bytes, of the Info
buffer.
@param Info Caller allocated buffer that returns information
about ModeNumber.
@retval EFI_SUCCESS Mode information returned.
@retval EFI_BUFFER_TOO_SMALL The Info buffer was too small.
@retval EFI_DEVICE_ERROR A hardware error occurred trying to retrieve the
video mode.
@retval EFI_NOT_STARTED Video display is not initialized. Call SetMode ()
@retval EFI_INVALID_PARAMETER One of the input args was NULL.
**/
EFI_STATUS
EFIAPI
FbGopGraphicsOutputQueryMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN UINT32 ModeNumber,
OUT UINTN *SizeOfInfo,
OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info
);
/**
Graphics Output protocol interface to set video mode.
@param This Protocol instance pointer.
@param ModeNumber The mode number to be set.
@retval EFI_SUCCESS Graphics mode was changed.
@retval EFI_DEVICE_ERROR The device had an error and could not complete the
request.
@retval EFI_UNSUPPORTED ModeNumber is not supported by this device.
**/
EFI_STATUS
EFIAPI
FbGopGraphicsOutputSetMode (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL * This,
IN UINT32 ModeNumber
);
/**
Graphics Output protocol instance to block transfer for VBE device.
@param This Pointer to Graphics Output protocol instance
@param BltBuffer The data to transfer to screen
@param BltOperation The operation to perform
@param SourceX The X coordinate of the source for BltOperation
@param SourceY The Y coordinate of the source for BltOperation
@param DestinationX The X coordinate of the destination for
BltOperation
@param DestinationY The Y coordinate of the destination for
BltOperation
@param Width The width of a rectangle in the blt rectangle in
pixels
@param Height The height of a rectangle in the blt rectangle in
pixels
@param Delta Not used for EfiBltVideoFill and
EfiBltVideoToVideo operation. If a Delta of 0 is
used, the entire BltBuffer will be operated on. If
a subrectangle of the BltBuffer is used, then
Delta represents the number of bytes in a row of
the BltBuffer.
@retval EFI_INVALID_PARAMETER Invalid parameter passed in
@retval EFI_SUCCESS Blt operation success
**/
EFI_STATUS
EFIAPI
FbGopGraphicsOutputVbeBlt (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta
);
/**
Graphics Output protocol instance to block transfer for VGA device.
@param This Pointer to Graphics Output protocol instance
@param BltBuffer The data to transfer to screen
@param BltOperation The operation to perform
@param SourceX The X coordinate of the source for BltOperation
@param SourceY The Y coordinate of the source for BltOperation
@param DestinationX The X coordinate of the destination for
BltOperation
@param DestinationY The Y coordinate of the destination for
BltOperation
@param Width The width of a rectangle in the blt rectangle in
pixels
@param Height The height of a rectangle in the blt rectangle in
pixels
@param Delta Not used for EfiBltVideoFill and
EfiBltVideoToVideo operation. If a Delta of 0 is
used, the entire BltBuffer will be operated on. If
a subrectangle of the BltBuffer is used, then
Delta represents the number of bytes in a row of
the BltBuffer.
@retval EFI_INVALID_PARAMETER Invalid parameter passed in
@retval EFI_SUCCESS Blt operation success
**/
EFI_STATUS
EFIAPI
FbGopGraphicsOutputVgaBlt (
IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL
IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation,
IN UINTN SourceX,
IN UINTN SourceY,
IN UINTN DestinationX,
IN UINTN DestinationY,
IN UINTN Width,
IN UINTN Height,
IN UINTN Delta
);
/**
Install child handles if the Handle supports MBR format.
@param This Calling context.
@param ParentHandle Parent Handle
@param ParentPciIo Parent PciIo interface
@param ParentLegacyBios Parent LegacyBios interface
@param ParentDevicePath Parent Device Path
@param RemainingDevicePath Remaining Device Path
@retval EFI_SUCCESS If a child handle was added
@retval other A child handle was not added
**/
EFI_STATUS
FbGopChildHandleInstall (
IN EFI_DRIVER_BINDING_PROTOCOL *This,
IN EFI_HANDLE ParentHandle,
IN EFI_PCI_IO_PROTOCOL *ParentPciIo,
IN VOID *ParentLegacyBios,
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
);
/**
Deregister an video child handle and free resources.
@param This Protocol instance pointer.
@param Controller Video controller handle
@param Handle Video child handle
@return EFI_STATUS
**/
EFI_STATUS
FbGopChildHandleUninstall (
EFI_DRIVER_BINDING_PROTOCOL *This,
EFI_HANDLE Controller,
EFI_HANDLE Handle
);
/**
Release resource for bios video instance.
@param FbGopPrivate Video child device private data structure
**/
VOID
FbGopDeviceReleaseResource (
FB_VIDEO_DEV *FbGopPrivate
);
/**
Check if all video child handles have been uninstalled.
@param Controller Video controller handle
@return TRUE Child handles exist.
@return FALSE All video child handles have been uninstalled.
**/
BOOLEAN
HasChildHandle (
IN EFI_HANDLE Controller
);
#endif

63
CorebootPayloadPkg/FbGop/FbGop.inf
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@ -1,63 +0,0 @@
## @file
# Video driver based on legacy bios.
#
# This driver by using Legacy Bios protocol service to support csm Video
# and produce Graphics Output Protocol.
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = FbGop
FILE_GUID = 0B04B2ED-861C-42cd-A22F-C3AAFACCB896
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
ENTRY_POINT = FbGopEntryPoint
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
# DRIVER_BINDING = gBiosVideoDriverBinding
# COMPONENT_NAME = gBiosVideoComponentName
#
[Sources]
FbGop.c
FbGop.h
ComponentName.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
CorebootModulePkg/CorebootModulePkg.dec
[LibraryClasses]
MemoryAllocationLib
DevicePathLib
UefiLib
UefiBootServicesTableLib
UefiDriverEntryPoint
BaseMemoryLib
ReportStatusCodeLib
DebugLib
PcdLib
HobLib
[Guids]
gUefiFrameBufferInfoGuid
[Protocols]
gEfiGraphicsOutputProtocolGuid # PROTOCOL BY_START
gEfiPciIoProtocolGuid # PROTOCOL TO_START
gEfiDevicePathProtocolGuid # PROTOCOL TO_START
gEfiEdidDiscoveredProtocolGuid
gEfiEdidActiveProtocolGuid

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CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c
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@ -1,270 +0,0 @@
/** @file
ACPI Timer implements one instance of Timer Library.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/TimerLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Guid/AcpiBoardInfoGuid.h>
#include <IndustryStandard/Acpi.h>
#define ACPI_TIMER_COUNT_SIZE BIT24
UINTN mPmTimerReg = 0;
/**
The constructor function enables ACPI IO space.
If ACPI I/O space not enabled, this function will enable it.
It will always return RETURN_SUCCESS.
@retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
**/
RETURN_STATUS
EFIAPI
AcpiTimerLibConstructor (
VOID
)
{
EFI_HOB_GUID_TYPE *GuidHob;
ACPI_BOARD_INFO *pAcpiBoardInfo;
//
// Find the acpi board information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
mPmTimerReg = (UINTN)pAcpiBoardInfo->PmTimerRegBase;
return EFI_SUCCESS;
}
/**
Internal function to read the current tick counter of ACPI.
Internal function to read the current tick counter of ACPI.
@return The tick counter read.
**/
UINT32
InternalAcpiGetTimerTick (
VOID
)
{
if (mPmTimerReg == 0)
AcpiTimerLibConstructor ();
return IoRead32 (mPmTimerReg);
}
/**
Stalls the CPU for at least the given number of ticks.
Stalls the CPU for at least the given number of ticks. It's invoked by
MicroSecondDelay() and NanoSecondDelay().
@param Delay A period of time to delay in ticks.
**/
VOID
InternalAcpiDelay (
IN UINT32 Delay
)
{
UINT32 Ticks;
UINT32 Times;
Times = Delay >> 22;
Delay &= BIT22 - 1;
do {
//
// The target timer count is calculated here
//
Ticks = InternalAcpiGetTimerTick () + Delay;
Delay = BIT22;
//
// Wait until time out
// Delay >= 2^23 could not be handled by this function
// Timer wrap-arounds are handled correctly by this function
//
while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
CpuPause ();
}
} while (Times-- > 0);
}
/**
Stalls the CPU for at least the given number of microseconds.
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@param MicroSeconds The minimum number of microseconds to delay.
@return MicroSeconds
**/
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
)
{
InternalAcpiDelay (
(UINT32)DivU64x32 (
MultU64x32 (
MicroSeconds,
ACPI_TIMER_FREQUENCY
),
1000000u
)
);
return MicroSeconds;
}
/**
Stalls the CPU for at least the given number of nanoseconds.
Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
@param NanoSeconds The minimum number of nanoseconds to delay.
@return NanoSeconds
**/
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
InternalAcpiDelay (
(UINT32)DivU64x32 (
MultU64x32 (
NanoSeconds,
ACPI_TIMER_FREQUENCY
),
1000000000u
)
);
return NanoSeconds;
}
/**
Retrieves the current value of a 64-bit free running performance counter.
Retrieves the current value of a 64-bit free running performance counter. The
counter can either count up by 1 or count down by 1. If the physical
performance counter counts by a larger increment, then the counter values
must be translated. The properties of the counter can be retrieved from
GetPerformanceCounterProperties().
@return The current value of the free running performance counter.
**/
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return (UINT64)InternalAcpiGetTimerTick ();
}
/**
Retrieves the 64-bit frequency in Hz and the range of performance counter
values.
If StartValue is not NULL, then the value that the performance counter starts
with immediately after is it rolls over is returned in StartValue. If
EndValue is not NULL, then the value that the performance counter end with
immediately before it rolls over is returned in EndValue. The 64-bit
frequency of the performance counter in Hz is always returned. If StartValue
is less than EndValue, then the performance counter counts up. If StartValue
is greater than EndValue, then the performance counter counts down. For
example, a 64-bit free running counter that counts up would have a StartValue
of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
@param StartValue The value the performance counter starts with when it
rolls over.
@param EndValue The value that the performance counter ends with before
it rolls over.
@return The frequency in Hz.
**/
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
*StartValue = 0;
}
if (EndValue != NULL) {
*EndValue = ACPI_TIMER_COUNT_SIZE - 1;
}
return ACPI_TIMER_FREQUENCY;
}
/**
Converts elapsed ticks of performance counter to time in nanoseconds.
This function converts the elapsed ticks of running performance counter to
time value in unit of nanoseconds.
@param Ticks The number of elapsed ticks of running performance counter.
@return The elapsed time in nanoseconds.
**/
UINT64
EFIAPI
GetTimeInNanoSecond (
IN UINT64 Ticks
)
{
UINT64 Frequency;
UINT64 NanoSeconds;
UINT64 Remainder;
INTN Shift;
Frequency = GetPerformanceCounterProperties (NULL, NULL);
//
// Ticks
// Time = --------- x 1,000,000,000
// Frequency
//
NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);
//
// Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
// Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
// i.e. highest bit set in Remainder should <= 33.
//
Shift = MAX (0, HighBitSet64 (Remainder) - 33);
Remainder = RShiftU64 (Remainder, (UINTN) Shift);
Frequency = RShiftU64 (Frequency, (UINTN) Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds;
}

40
CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf
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@ -1,40 +0,0 @@
## @file
# ACPI Timer Library Instance.
#
# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = AcpiTimerLib
FILE_GUID = A41BF616-EF77-4658-9992-D813071C34CF
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib
CONSTRUCTOR = AcpiTimerLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
AcpiTimerLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
CorebootModulePkg/CorebootModulePkg.dec
[LibraryClasses]
BaseLib
IoLib
HobLib
DebugLib
[Guids]
gUefiAcpiBoardInfoGuid

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CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
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/** @file
Header file of PciHostBridgeLib.
Copyright (C) 2016, Red Hat, Inc.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PCI_HOST_BRIDGE_H
#define _PCI_HOST_BRIDGE_H
typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;
PCI_ROOT_BRIDGE *
ScanForRootBridges (
UINTN *NumberOfRootBridges
);
/**
Initialize a PCI_ROOT_BRIDGE structure.
@param[in] Supports Supported attributes.
@param[in] Attributes Initial attributes.
@param[in] AllocAttributes Allocation attributes.
@param[in] RootBusNumber The bus number to store in RootBus.
@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
assigned to any subordinate bus found behind any
PCI bridge hanging off this root bus.
The caller is responsible for ensuring that
RootBusNumber <= MaxSubBusNumber. If
RootBusNumber equals MaxSubBusNumber, then the
root bus has no room for subordinate buses.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
caller) that should be filled in by this
function.
@retval EFI_SUCCESS Initialization successful. A device path
consisting of an ACPI device path node, with
UID = RootBusNumber, has been allocated and
linked into RootBus.
@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
**/
EFI_STATUS
InitRootBridge (
IN UINT64 Supports,
IN UINT64 Attributes,
IN UINT64 AllocAttributes,
IN UINT8 RootBusNumber,
IN UINT8 MaxSubBusNumber,
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
OUT PCI_ROOT_BRIDGE *RootBus
);
#endif

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CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
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/** @file
Library instance of PciHostBridgeLib library class for coreboot.
Copyright (C) 2016, Red Hat, Inc.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <IndustryStandard/Pci.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PciHostBridgeLib.h>
#include <Library/PciLib.h>
#include "PciHostBridge.h"
STATIC
CONST
CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
{
{
ACPI_DEVICE_PATH,
ACPI_DP,
{
(UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
(UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
}
},
EISA_PNP_ID(0x0A03), // HID
0 // UID
},
{
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{
END_DEVICE_PATH_LENGTH,
0
}
}
};
/**
Initialize a PCI_ROOT_BRIDGE structure.
@param[in] Supports Supported attributes.
@param[in] Attributes Initial attributes.
@param[in] AllocAttributes Allocation attributes.
@param[in] RootBusNumber The bus number to store in RootBus.
@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
assigned to any subordinate bus found behind any
PCI bridge hanging off this root bus.
The caller is responsible for ensuring that
RootBusNumber <= MaxSubBusNumber. If
RootBusNumber equals MaxSubBusNumber, then the
root bus has no room for subordinate buses.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
caller) that should be filled in by this
function.
@retval EFI_SUCCESS Initialization successful. A device path
consisting of an ACPI device path node, with
UID = RootBusNumber, has been allocated and
linked into RootBus.
@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
**/
EFI_STATUS
InitRootBridge (
IN UINT64 Supports,
IN UINT64 Attributes,
IN UINT64 AllocAttributes,
IN UINT8 RootBusNumber,
IN UINT8 MaxSubBusNumber,
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
OUT PCI_ROOT_BRIDGE *RootBus
)
{
CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
//
// Be safe if other fields are added to PCI_ROOT_BRIDGE later.
//
ZeroMem (RootBus, sizeof *RootBus);
RootBus->Segment = 0;
RootBus->Supports = Supports;
RootBus->Attributes = Attributes;
RootBus->DmaAbove4G = FALSE;
RootBus->AllocationAttributes = AllocAttributes;
RootBus->Bus.Base = RootBusNumber;
RootBus->Bus.Limit = MaxSubBusNumber;
CopyMem (&RootBus->Io, Io, sizeof (*Io));
CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));
CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));
RootBus->NoExtendedConfigSpace = FALSE;
DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
&mRootBridgeDevicePathTemplate);
if (DevicePath == NULL) {
DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
return EFI_OUT_OF_RESOURCES;
}
DevicePath->AcpiDevicePath.UID = RootBusNumber;
RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
DEBUG ((EFI_D_INFO,
"%a: populated root bus %d, with room for %d subordinate bus(es)\n",
__FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
return EFI_SUCCESS;
}
/**
Return all the root bridge instances in an array.
@param Count Return the count of root bridge instances.
@return All the root bridge instances in an array.
The array should be passed into PciHostBridgeFreeRootBridges()
when it's not used.
**/
PCI_ROOT_BRIDGE *
EFIAPI
PciHostBridgeGetRootBridges (
UINTN *Count
)
{
return ScanForRootBridges (Count);
}
/**
Free the root bridge instances array returned from
PciHostBridgeGetRootBridges().
@param The root bridge instances array.
@param The count of the array.
**/
VOID
EFIAPI
PciHostBridgeFreeRootBridges (
PCI_ROOT_BRIDGE *Bridges,
UINTN Count
)
{
if (Bridges == NULL && Count == 0) {
return;
}
ASSERT (Bridges != NULL && Count > 0);
do {
--Count;
FreePool (Bridges[Count].DevicePath);
} while (Count > 0);
FreePool (Bridges);
}
/**
Inform the platform that the resource conflict happens.
@param HostBridgeHandle Handle of the Host Bridge.
@param Configuration Pointer to PCI I/O and PCI memory resource
descriptors. The Configuration contains the resources
for all the root bridges. The resource for each root
bridge is terminated with END descriptor and an
additional END is appended indicating the end of the
entire resources. The resource descriptor field
values follow the description in
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
.SubmitResources().
**/
VOID
EFIAPI
PciHostBridgeResourceConflict (
EFI_HANDLE HostBridgeHandle,
VOID *Configuration
)
{
//
// coreboot UEFI Payload does not do PCI enumeration and should not call this
// library interface.
//
ASSERT (FALSE);
}

41
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
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@ -1,41 +0,0 @@
## @file
# Library instance of PciHostBridgeLib library class for coreboot.
#
# Copyright (C) 2016, Red Hat, Inc.
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PciHostBridgeLib
FILE_GUID = 62EE5269-CFFD-43a3-BE3F-622FC79F467E
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PciHostBridgeLib
#
# The following information is for reference only and not required by the build
# tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
PciHostBridge.h
PciHostBridgeLib.c
PciHostBridgeSupport.c
[Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
BaseMemoryLib
DebugLib
DevicePathLib
MemoryAllocationLib
PciLib

584
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
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@ -1,584 +0,0 @@
/** @file
Scan the entire PCI bus for root bridges to support coreboot UEFI payload.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <IndustryStandard/Pci.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PciHostBridgeLib.h>
#include <Library/PciLib.h>
#include "PciHostBridge.h"
/**
Adjust the collected PCI resource.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
**/
VOID
AdjustRootBridgeResource (
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
)
{
UINT64 Mask;
//
// For now try to downgrade everything into MEM32 since
// - coreboot does not assign resource above 4GB
// - coreboot might allocate interleaved MEM32 and PMEM32 resource
// in some cases
//
if (PMem->Base < Mem->Base) {
Mem->Base = PMem->Base;
}
if (PMem->Limit > Mem->Limit) {
Mem->Limit = PMem->Limit;
}
PMem->Base = MAX_UINT64;
PMem->Limit = 0;
if (MemAbove4G->Base < 0x100000000ULL) {
if (MemAbove4G->Base < Mem->Base) {
Mem->Base = MemAbove4G->Base;
}
if (MemAbove4G->Limit > Mem->Limit) {
Mem->Limit = MemAbove4G->Limit;
}
MemAbove4G->Base = MAX_UINT64;
MemAbove4G->Limit = 0;
}
if (PMemAbove4G->Base < 0x100000000ULL) {
if (PMemAbove4G->Base < Mem->Base) {
Mem->Base = PMemAbove4G->Base;
}
if (PMemAbove4G->Limit > Mem->Limit) {
Mem->Limit = PMemAbove4G->Limit;
}
PMemAbove4G->Base = MAX_UINT64;
PMemAbove4G->Limit = 0;
}
//
// Align IO resource at 4K boundary
//
Mask = 0xFFFULL;
Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;
if (Io->Base != MAX_UINT64) {
Io->Base &= ~Mask;
}
//
// Align MEM resource at 1MB boundary
//
Mask = 0xFFFFFULL;
Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;
if (Mem->Base != MAX_UINT64) {
Mem->Base &= ~Mask;
}
}
/**
Probe a bar is existed or not.
@param[in] Address PCI address for the BAR.
@param[out] OriginalValue The original bar value returned.
@param[out] Value The probed bar value returned.
**/
STATIC
VOID
PcatPciRootBridgeBarExisted (
IN UINT64 Address,
OUT UINT32 *OriginalValue,
OUT UINT32 *Value
)
{
UINTN PciAddress;
PciAddress = (UINTN)Address;
//
// Preserve the original value
//
*OriginalValue = PciRead32 (PciAddress);
//
// Disable timer interrupt while the BAR is probed
//
DisableInterrupts ();
PciWrite32 (PciAddress, 0xFFFFFFFF);
*Value = PciRead32 (PciAddress);
PciWrite32 (PciAddress, *OriginalValue);
//
// Enable interrupt
//
EnableInterrupts ();
}
/**
Parse PCI bar and collect the assigned PCI resource information.
@param[in] Command Supported attributes.
@param[in] Bus PCI bus number.
@param[in] Device PCI device number.
@param[in] Function PCI function number.
@param[in] BarOffsetBase PCI bar start offset.
@param[in] BarOffsetEnd PCI bar end offset.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
**/
STATIC
VOID
PcatPciRootBridgeParseBars (
IN UINT16 Command,
IN UINTN Bus,
IN UINTN Device,
IN UINTN Function,
IN UINTN BarOffsetBase,
IN UINTN BarOffsetEnd,
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
)
{
UINT32 OriginalValue;
UINT32 Value;
UINT32 OriginalUpperValue;
UINT32 UpperValue;
UINT64 Mask;
UINTN Offset;
UINTN LowBit;
UINT64 Base;
UINT64 Length;
UINT64 Limit;
PCI_ROOT_BRIDGE_APERTURE *MemAperture;
for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {
PcatPciRootBridgeBarExisted (
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
&OriginalValue, &Value
);
if (Value == 0) {
continue;
}
if ((Value & BIT0) == BIT0) {
//
// IO Bar
//
if (Command & EFI_PCI_COMMAND_IO_SPACE) {
Mask = 0xfffffffc;
Base = OriginalValue & Mask;
Length = ((~(Value & Mask)) & Mask) + 0x04;
if (!(Value & 0xFFFF0000)) {
Length &= 0x0000FFFF;
}
Limit = Base + Length - 1;
if ((Base > 0) && (Base < Limit)) {
if (Io->Base > Base) {
Io->Base = Base;
}
if (Io->Limit < Limit) {
Io->Limit = Limit;
}
}
}
} else {
//
// Mem Bar
//
if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
Mask = 0xfffffff0;
Base = OriginalValue & Mask;
Length = Value & Mask;
if ((Value & (BIT1 | BIT2)) == 0) {
//
// 32bit
//
Length = ((~Length) + 1) & 0xffffffff;
if ((Value & BIT3) == BIT3) {
MemAperture = PMem;
} else {
MemAperture = Mem;
}
} else {
//
// 64bit
//
Offset += 4;
PcatPciRootBridgeBarExisted (
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
&OriginalUpperValue,
&UpperValue
);
Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
if (Length != 0) {
LowBit = LowBitSet64 (Length);
Length = LShiftU64 (1ULL, LowBit);
}
if ((Value & BIT3) == BIT3) {
MemAperture = PMemAbove4G;
} else {
MemAperture = MemAbove4G;
}
}
Limit = Base + Length - 1;
if ((Base > 0) && (Base < Limit)) {
if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}
if (MemAperture->Limit < Limit) {
MemAperture->Limit = Limit;
}
}
}
}
}
}
/**
Scan for all root bridges in platform.
@param[out] NumberOfRootBridges Number of root bridges detected
@retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
**/
PCI_ROOT_BRIDGE *
ScanForRootBridges (
OUT UINTN *NumberOfRootBridges
)
{
UINTN PrimaryBus;
UINTN SubBus;
UINT8 Device;
UINT8 Function;
UINTN NumberOfDevices;
UINTN Address;
PCI_TYPE01 Pci;
UINT64 Attributes;
UINT64 Base;
UINT64 Limit;
UINT64 Value;
PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;
PCI_ROOT_BRIDGE *RootBridges;
UINTN BarOffsetEnd;
*NumberOfRootBridges = 0;
RootBridges = NULL;
//
// After scanning all the PCI devices on the PCI root bridge's primary bus,
// update the Primary Bus Number for the next PCI root bridge to be this PCI
// root bridge's subordinate bus number + 1.
//
for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
SubBus = PrimaryBus;
Attributes = 0;
ZeroMem (&Io, sizeof (Io));
ZeroMem (&Mem, sizeof (Mem));
ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
ZeroMem (&PMem, sizeof (PMem));
ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
//
// Scan all the PCI devices on the primary bus of the PCI root bridge
//
for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
//
// Compute the PCI configuration address of the PCI device to probe
//
Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);
//
// Read the Vendor ID from the PCI Configuration Header
//
if (PciRead16 (Address) == MAX_UINT16) {
if (Function == 0) {
//
// If the PCI Configuration Read fails, or a PCI device does not
// exist, then skip this entire PCI device
//
break;
} else {
//
// If PCI function != 0, VendorId == 0xFFFF, we continue to search
// PCI function.
//
continue;
}
}
//
// Read the entire PCI Configuration Header
//
PciReadBuffer (Address, sizeof (Pci), &Pci);
//
// Increment the number of PCI device found on the primary bus of the
// PCI root bridge
//
NumberOfDevices++;
//
// Look for devices with the VGA Palette Snoop enabled in the COMMAND
// register of the PCI Config Header
//
if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
}
BarOffsetEnd = 0;
//
// PCI-PCI Bridge
//
if (IS_PCI_BRIDGE (&Pci)) {
//
// Get the Bus range that the PPB is decoding
//
if (Pci.Bridge.SubordinateBus > SubBus) {
//
// If the subordinate bus number of the PCI-PCI bridge is greater
// than the PCI root bridge's current subordinate bus number,
// then update the PCI root bridge's subordinate bus number
//
SubBus = Pci.Bridge.SubordinateBus;
}
//
// Get the I/O range that the PPB is decoding
//
Value = Pci.Bridge.IoBase & 0x0f;
Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
if (Value == BIT0) {
Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
}
if ((Base > 0) && (Base < Limit)) {
if (Io.Base > Base) {
Io.Base = Base;
}
if (Io.Limit < Limit) {
Io.Limit = Limit;
}
}
//
// Get the Memory range that the PPB is decoding
//
Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
if ((Base > 0) && (Base < Limit)) {
if (Mem.Base > Base) {
Mem.Base = Base;
}
if (Mem.Limit < Limit) {
Mem.Limit = Limit;
}
}
//
// Get the Prefetchable Memory range that the PPB is decoding
//
Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
<< 16) | 0xfffff;
MemAperture = &PMem;
if (Value == BIT0) {
Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
MemAperture = &PMemAbove4G;
}
if ((Base > 0) && (Base < Limit)) {
if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}
if (MemAperture->Limit < Limit) {
MemAperture->Limit = Limit;
}
}
//
// Look at the PPB Configuration for legacy decoding attributes
//
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
== EFI_PCI_BRIDGE_CONTROL_ISA) {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
== EFI_PCI_BRIDGE_CONTROL_VGA) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
!= 0) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
}
}
BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);
} else {
//
// Parse the BARs of the PCI device to get what I/O Ranges, Memory
// Ranges, and Prefetchable Memory Ranges the device is decoding
//
if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);
}
}
PcatPciRootBridgeParseBars (
Pci.Hdr.Command,
PrimaryBus,
Device,
Function,
OFFSET_OF (PCI_TYPE00, Device.Bar),
BarOffsetEnd,
&Io,
&Mem, &MemAbove4G,
&PMem, &PMemAbove4G
);
//
// See if the PCI device is an IDE controller
//
if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
PCI_CLASS_MASS_STORAGE_IDE)) {
if (Pci.Hdr.ClassCode[0] & 0x80) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
if (Pci.Hdr.ClassCode[0] & 0x01) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
}
if (Pci.Hdr.ClassCode[0] & 0x04) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
}
//
// See if the PCI device is a legacy VGA controller or
// a standard VGA controller
//
if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
}
//
// See if the PCI Device is a PCI - ISA or PCI - EISA
// or ISA_POSITIVE_DECODE Bridge device
//
if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
}
//
// If this device is not a multi function device, then skip the rest
// of this PCI device
//
if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
break;
}
}
}
//
// If at least one PCI device was found on the primary bus of this PCI
// root bridge, then the PCI root bridge exists.
//
if (NumberOfDevices > 0) {
RootBridges = ReallocatePool (
(*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
(*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
RootBridges
);
ASSERT (RootBridges != NULL);
AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);
InitRootBridge (
Attributes, Attributes, 0,
(UINT8) PrimaryBus, (UINT8) SubBus,
&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
&RootBridges[*NumberOfRootBridges]
);
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
//
// Increment the index for the next PCI Root Bridge
//
(*NumberOfRootBridges)++;
}
}
return RootBridges;
}

265
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
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@ -1,265 +0,0 @@
/** @file
This file include all platform action which can be customized
by IBV/OEM.
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PlatformBootManager.h"
#include "PlatformConsole.h"
VOID
InstallReadyToLock (
VOID
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
DEBUG((DEBUG_INFO,"InstallReadyToLock entering......\n"));
//
// Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter
// Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth
//
EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n"));
//
// Install DxeSmmReadyToLock protocol in order to lock SMM
//
Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **) &SmmAccess);
if (!EFI_ERROR (Status)) {
Handle = NULL;
Status = gBS->InstallProtocolInterface (
&Handle,
&gEfiDxeSmmReadyToLockProtocolGuid,
EFI_NATIVE_INTERFACE,
NULL
);
ASSERT_EFI_ERROR (Status);
}
DEBUG((DEBUG_INFO,"InstallReadyToLock end\n"));
return;
}
/**
Return the index of the load option in the load option array.
The function consider two load options are equal when the
OptionType, Attributes, Description, FilePath and OptionalData are equal.
@param Key Pointer to the load option to be found.
@param Array Pointer to the array of load options to be found.
@param Count Number of entries in the Array.
@retval -1 Key wasn't found in the Array.
@retval 0 ~ Count-1 The index of the Key in the Array.
**/
INTN
PlatformFindLoadOption (
IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
IN UINTN Count
)
{
UINTN Index;
for (Index = 0; Index < Count; Index++) {
if ((Key->OptionType == Array[Index].OptionType) &&
(Key->Attributes == Array[Index].Attributes) &&
(StrCmp (Key->Description, Array[Index].Description) == 0) &&
(CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
(Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
(CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
return (INTN) Index;
}
}
return -1;
}
/**
Register a boot option using a file GUID in the FV.
@param FileGuid The file GUID name in FV.
@param Description The boot option description.
@param Attributes The attributes used for the boot option loading.
**/
VOID
PlatformRegisterFvBootOption (
EFI_GUID *FileGuid,
CHAR16 *Description,
UINT32 Attributes
)
{
EFI_STATUS Status;
UINTN OptionIndex;
EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
UINTN BootOptionCount;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);
ASSERT_EFI_ERROR (Status);
EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
DevicePath = AppendDevicePathNode (
DevicePathFromHandle (LoadedImage->DeviceHandle),
(EFI_DEVICE_PATH_PROTOCOL *) &FileNode
);
Status = EfiBootManagerInitializeLoadOption (
&NewOption,
LoadOptionNumberUnassigned,
LoadOptionTypeBoot,
Attributes,
Description,
DevicePath,
NULL,
0
);
if (!EFI_ERROR (Status)) {
BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);
OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
if (OptionIndex == -1) {
Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);
ASSERT_EFI_ERROR (Status);
}
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
}
/**
Do the platform specific action before the console is connected.
Such as:
Update console variable;
Register new Driver#### or Boot####;
Signal ReadyToLock event.
**/
VOID
EFIAPI
PlatformBootManagerBeforeConsole (
VOID
)
{
EFI_INPUT_KEY Enter;
EFI_INPUT_KEY F2;
EFI_INPUT_KEY Down;
EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
PlatformConsoleInit ();
//
// Register ENTER as CONTINUE key
//
Enter.ScanCode = SCAN_NULL;
Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
//
// Map F2 to Boot Manager Menu
//
F2.ScanCode = SCAN_F2;
F2.UnicodeChar = CHAR_NULL;
EfiBootManagerGetBootManagerMenu (&BootOption);
EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);
//
// Also add Down key to Boot Manager Menu since some serial terminals don't support F2 key.
//
Down.ScanCode = SCAN_DOWN;
Down.UnicodeChar = CHAR_NULL;
EfiBootManagerGetBootManagerMenu (&BootOption);
EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL);
//
// Install ready to lock.
// This needs to be done before option rom dispatched.
//
InstallReadyToLock ();
//
// Dispatch deferred images after EndOfDxe event and ReadyToLock installation.
//
EfiBootManagerDispatchDeferredImages ();
}
/**
Do the platform specific action after the console is connected.
Such as:
Dynamically switch output mode;
Signal console ready platform customized event;
Run diagnostics like memory testing;
Connect certain devices;
Dispatch additional option roms.
**/
VOID
EFIAPI
PlatformBootManagerAfterConsole (
VOID
)
{
EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;
Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;
White.Blue = White.Green = White.Red = White.Reserved = 0xFF;
EfiBootManagerConnectAll ();
EfiBootManagerRefreshAllBootOption ();
//
// Register UEFI Shell
//
PlatformRegisterFvBootOption (PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE);
Print (
L"\n"
L"F2 or Down to enter Boot Manager Menu.\n"
L"ENTER to boot directly.\n"
L"\n"
);
}
/**
This function is called each second during the boot manager waits the timeout.
@param TimeoutRemain The remaining timeout.
**/
VOID
EFIAPI
PlatformBootManagerWaitCallback (
UINT16 TimeoutRemain
)
{
return;
}
/**
The function is called when no boot option could be launched,
including platform recovery options and options pointing to applications
built into firmware volumes.
If this function returns, BDS attempts to enter an infinite loop.
**/
VOID
EFIAPI
PlatformBootManagerUnableToBoot (
VOID
)
{
return;
}

121
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
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@ -1,121 +0,0 @@
/**@file
Head file for BDS Platform specific code
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PLATFORM_BOOT_MANAGER_H
#define _PLATFORM_BOOT_MANAGER_H
#include <PiDxe.h>
#include <Protocol/LoadedImage.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootManagerLib.h>
#include <Library/PcdLib.h>
#include <Library/DevicePathLib.h>
#include <Library/HiiLib.h>
#include <Library/PrintLib.h>
#include <Library/DxeServicesLib.h>
#include <Library/BootLogoLib.h>
#include <Protocol/SmmAccess2.h>
typedef struct {
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ConnectType;
} PLATFORM_CONSOLE_CONNECT_ENTRY;
extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
#define gEndEntire \
{ \
END_DEVICE_PATH_TYPE,\
END_ENTIRE_DEVICE_PATH_SUBTYPE,\
{ END_DEVICE_PATH_LENGTH, 0 },\
}
#define CONSOLE_OUT BIT0
#define CONSOLE_IN BIT1
#define STD_ERROR BIT2
typedef struct {
VENDOR_DEVICE_PATH VendorDevicePath;
UINT32 Instance;
} WIN_NT_VENDOR_DEVICE_PATH_NODE;
//
// Below is the platform console device path
//
typedef struct {
VENDOR_DEVICE_PATH NtBus;
WIN_NT_VENDOR_DEVICE_PATH_NODE SerialDevice;
UART_DEVICE_PATH Uart;
VENDOR_DEVICE_PATH TerminalType;
EFI_DEVICE_PATH_PROTOCOL End;
} NT_ISA_SERIAL_DEVICE_PATH;
typedef struct {
VENDOR_DEVICE_PATH NtBus;
WIN_NT_VENDOR_DEVICE_PATH_NODE NtGopDevice;
EFI_DEVICE_PATH_PROTOCOL End;
} NT_PLATFORM_GOP_DEVICE_PATH;
/**
Use SystemTable Conout to stop video based Simple Text Out consoles from going
to the video device. Put up LogoFile on every video device that is a console.
@param[in] LogoFile File name of logo to display on the center of the screen.
@retval EFI_SUCCESS ConsoleControl has been flipped to graphics and logo displayed.
@retval EFI_UNSUPPORTED Logo not found
**/
EFI_STATUS
PlatformBootManagerEnableQuietBoot (
IN EFI_GUID *LogoFile
);
/**
Use SystemTable Conout to turn on video based Simple Text Out consoles. The
Simple Text Out screens will now be synced up with all non video output devices
@retval EFI_SUCCESS UGA devices are back in text mode and synced up.
**/
EFI_STATUS
PlatformBootManagerDisableQuietBoot (
VOID
);
/**
Show progress bar with title above it. It only works in Graphics mode.
@param TitleForeground Foreground color for Title.
@param TitleBackground Background color for Title.
@param Title Title above progress bar.
@param ProgressColor Progress bar color.
@param Progress Progress (0-100)
@param PreviousValue The previous value of the progress.
@retval EFI_STATUS Success update the progress bar
**/
EFI_STATUS
PlatformBootManagerShowProgress (
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
IN CHAR16 *Title,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
IN UINTN Progress,
IN UINTN PreviousValue
);
#endif // _PLATFORM_BOOT_MANAGER_H

74
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
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@ -1,74 +0,0 @@
## @file
# Include all platform action which can be customized by IBV/OEM.
#
# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformBootManagerLib
FILE_GUID = F0D9063A-DADB-4185-85E2-D7ACDA93F7A6
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
PlatformData.c
PlatformConsole.c
PlatformConsole.h
PlatformBootManager.c
PlatformBootManager.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
CorebootPayloadPkg/CorebootPayloadPkg.dec
[LibraryClasses]
BaseLib
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
UefiLib
UefiBootManagerLib
PcdLib
DxeServicesLib
MemoryAllocationLib
DevicePathLib
HiiLib
PrintLib
PlatformHookLib
[Guids]
gEfiEndOfDxeEventGroupGuid
[Protocols]
gEfiGenericMemTestProtocolGuid ## CONSUMES
gEfiGraphicsOutputProtocolGuid ## CONSUMES
gEfiUgaDrawProtocolGuid ## CONSUMES
gEfiBootLogoProtocolGuid ## CONSUMES
gEfiDxeSmmReadyToLockProtocolGuid
gEfiSmmAccess2ProtocolGuid
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootlogoOnlyEnable
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits

611
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c
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@ -1,611 +0,0 @@
/** @file
This file include all platform action which can be customized by IBV/OEM.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PlatformBootManager.h"
#include "PlatformConsole.h"
#define PCI_DEVICE_PATH_NODE(Func, Dev) \
{ \
{ \
HARDWARE_DEVICE_PATH, \
HW_PCI_DP, \
{ \
(UINT8) (sizeof (PCI_DEVICE_PATH)), \
(UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
} \
}, \
(Func), \
(Dev) \
}
#define PNPID_DEVICE_PATH_NODE(PnpId) \
{ \
{ \
ACPI_DEVICE_PATH, \
ACPI_DP, \
{ \
(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
}, \
}, \
EISA_PNP_ID((PnpId)), \
0 \
}
#define gPciRootBridge \
PNPID_DEVICE_PATH_NODE(0x0A03)
#define gPnp16550ComPort \
PNPID_DEVICE_PATH_NODE(0x0501)
#define gUartVendor \
{ \
{ \
HARDWARE_DEVICE_PATH, \
HW_VENDOR_DP, \
{ \
(UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
} \
}, \
{0xD3987D4B, 0x971A, 0x435F, {0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41}} \
}
#define gUart \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_UART_DP, \
{ \
(UINT8) (sizeof (UART_DEVICE_PATH)), \
(UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
} \
}, \
0, \
115200, \
8, \
1, \
1 \
}
#define gPcAnsiTerminal \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_VENDOR_DP, \
{ \
(UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
} \
}, \
DEVICE_PATH_MESSAGING_PC_ANSI \
}
ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort;
UART_DEVICE_PATH gUartDeviceNode = gUart;
VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal;
VENDOR_DEVICE_PATH gUartDeviceVendorNode = gUartVendor;
//
// Predefined platform root bridge
//
PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {
gPciRootBridge,
gEndEntire
};
EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = {
(EFI_DEVICE_PATH_PROTOCOL *) &gPlatformRootBridge0,
NULL
};
BOOLEAN mDetectVgaOnly;
/**
Add UART to ConOut, ConIn, ErrOut.
@param[in] DeviceHandle - LPC device path.
@retval EFI_SUCCESS - Serial console is added to ConOut, ConIn, and ErrOut.
@retval EFI_STATUS - No serial console is added.
**/
EFI_STATUS
PrepareLpcBridgeDevicePath (
IN EFI_HANDLE DeviceHandle
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
DevicePath = NULL;
Status = gBS->HandleProtocol (
DeviceHandle,
&gEfiDevicePathProtocolGuid,
(VOID*)&DevicePath
);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Register COM1
//
DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceVendorNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);
EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
return EFI_SUCCESS;
}
/**
Return the GOP device path in the platform.
@param[in] PciDevicePath - Device path for the PCI graphics device.
@param[out] GopDevicePath - Return the device path with GOP installed.
@retval EFI_SUCCESS - PCI VGA is added to ConOut.
@retval EFI_INVALID_PARAMETER - The device path parameter is invalid.
@retval EFI_STATUS - No GOP device found.
**/
EFI_STATUS
GetGopDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,
OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath
)
{
UINTN Index;
EFI_STATUS Status;
EFI_HANDLE PciDeviceHandle;
EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;
UINTN GopHandleCount;
EFI_HANDLE *GopHandleBuffer;
ACPI_ADR_DEVICE_PATH AcpiAdr;
EFI_DEVICE_PATH_PROTOCOL *MyDevicePath;
if (PciDevicePath == NULL || GopDevicePath == NULL) {
return EFI_INVALID_PARAMETER;
}
MyDevicePath = NULL;
//
// Initialize the GopDevicePath to be PciDevicePath
//
*GopDevicePath = PciDevicePath;
TempPciDevicePath = PciDevicePath;
Status = gBS->LocateDevicePath (
&gEfiDevicePathProtocolGuid,
&TempPciDevicePath,
&PciDeviceHandle
);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Try to connect this handle, so that GOP driver could start on this
// device and create child handles with GraphicsOutput Protocol installed
// on them, then we get device paths of these child handles and select
// them as possible console device.
//
AcpiAdr.Header.Type = ACPI_DEVICE_PATH;
AcpiAdr.Header.SubType = ACPI_ADR_DP;
AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, 8, 0);
SetDevicePathNodeLength (&AcpiAdr.Header, sizeof (ACPI_ADR_DEVICE_PATH));
MyDevicePath = AppendDevicePathNode(MyDevicePath, (EFI_DEVICE_PATH_PROTOCOL*)&AcpiAdr);
gBS->ConnectController (PciDeviceHandle, NULL, MyDevicePath, FALSE);
FreePool(MyDevicePath);
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiGraphicsOutputProtocolGuid,
NULL,
&GopHandleCount,
&GopHandleBuffer
);
if (!EFI_ERROR (Status)) {
//
// Add all the child handles as possible Console Device
//
for (Index = 0; Index < GopHandleCount; Index++) {
Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath);
if (EFI_ERROR (Status)) {
continue;
}
if (CompareMem (
PciDevicePath,
TempDevicePath,
GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH
) == 0) {
//
// In current implementation, we only enable one of the child handles
// as console device, i.e. sotre one of the child handle's device
// path to variable "ConOut"
// In future, we could select all child handles to be console device
//
*GopDevicePath = TempDevicePath;
//
// Delete the PCI device's path that added by GetPlugInPciVgaDevicePath()
// Add the integrity GOP device path.
//
EfiBootManagerUpdateConsoleVariable (ConOut, NULL, PciDevicePath);
EfiBootManagerUpdateConsoleVariable (ConOut, TempDevicePath, NULL);
}
}
gBS->FreePool (GopHandleBuffer);
}
return EFI_SUCCESS;
}
/**
Add PCI VGA to ConOut, ConIn, ErrOut.
@param[in] DeviceHandle - Handle of PciIo protocol.
@retval EFI_SUCCESS - PCI VGA is added to ConOut.
@retval EFI_STATUS - No PCI VGA device is added.
**/
EFI_STATUS
PreparePciVgaDevicePath (
IN EFI_HANDLE DeviceHandle
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;
DevicePath = NULL;
Status = gBS->HandleProtocol (
DeviceHandle,
&gEfiDevicePathProtocolGuid,
(VOID*)&DevicePath
);
if (EFI_ERROR (Status)) {
return Status;
}
GetGopDevicePath (DevicePath, &GopDevicePath);
DevicePath = GopDevicePath;
EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
return EFI_SUCCESS;
}
/**
Add PCI Serial to ConOut, ConIn, ErrOut.
@param[in] DeviceHandle - Handle of PciIo protocol.
@retval EFI_SUCCESS - PCI Serial is added to ConOut, ConIn, and ErrOut.
@retval EFI_STATUS - No PCI Serial device is added.
**/
EFI_STATUS
PreparePciSerialDevicePath (
IN EFI_HANDLE DeviceHandle
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
DevicePath = NULL;
Status = gBS->HandleProtocol (
DeviceHandle,
&gEfiDevicePathProtocolGuid,
(VOID*)&DevicePath
);
if (EFI_ERROR (Status)) {
return Status;
}
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);
EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
return EFI_SUCCESS;
}
/**
For every PCI instance execute a callback function.
@param[in] Id - The protocol GUID for callback
@param[in] CallBackFunction - The callback function
@param[in] Context - The context of the callback
@retval EFI_STATUS - Callback function failed.
**/
EFI_STATUS
EFIAPI
VisitAllInstancesOfProtocol (
IN EFI_GUID *Id,
IN PROTOCOL_INSTANCE_CALLBACK CallBackFunction,
IN VOID *Context
)
{
EFI_STATUS Status;
UINTN HandleCount;
EFI_HANDLE *HandleBuffer;
UINTN Index;
VOID *Instance;
//
// Start to check all the PciIo to find all possible device
//
HandleCount = 0;
HandleBuffer = NULL;
Status = gBS->LocateHandleBuffer (
ByProtocol,
Id,
NULL,
&HandleCount,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
return Status;
}
for (Index = 0; Index < HandleCount; Index++) {
Status = gBS->HandleProtocol (HandleBuffer[Index], Id, &Instance);
if (EFI_ERROR (Status)) {
continue;
}
Status = (*CallBackFunction) (
HandleBuffer[Index],
Instance,
Context
);
}
gBS->FreePool (HandleBuffer);
return EFI_SUCCESS;
}
/**
For every PCI instance execute a callback function.
@param[in] Handle - The PCI device handle
@param[in] Instance - The instance of the PciIo protocol
@param[in] Context - The context of the callback
@retval EFI_STATUS - Callback function failed.
**/
EFI_STATUS
EFIAPI
VisitingAPciInstance (
IN EFI_HANDLE Handle,
IN VOID *Instance,
IN VOID *Context
)
{
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
PCI_TYPE00 Pci;
PciIo = (EFI_PCI_IO_PROTOCOL*) Instance;
//
// Check for all PCI device
//
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint32,
0,
sizeof (Pci) / sizeof (UINT32),
&Pci
);
if (EFI_ERROR (Status)) {
return Status;
}
return (*(VISIT_PCI_INSTANCE_CALLBACK)(UINTN) Context) (
Handle,
PciIo,
&Pci
);
}
/**
For every PCI instance execute a callback function.
@param[in] CallBackFunction - Callback function pointer
@retval EFI_STATUS - Callback function failed.
**/
EFI_STATUS
EFIAPI
VisitAllPciInstances (
IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction
)
{
return VisitAllInstancesOfProtocol (
&gEfiPciIoProtocolGuid,
VisitingAPciInstance,
(VOID*)(UINTN) CallBackFunction
);
}
/**
Do platform specific PCI Device check and add them to
ConOut, ConIn, ErrOut.
@param[in] Handle - Handle of PCI device instance
@param[in] PciIo - PCI IO protocol instance
@param[in] Pci - PCI Header register block
@retval EFI_SUCCESS - PCI Device check and Console variable update successfully.
@retval EFI_STATUS - PCI Device check or Console variable update fail.
**/
EFI_STATUS
EFIAPI
DetectAndPreparePlatformPciDevicePath (
IN EFI_HANDLE Handle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN PCI_TYPE00 *Pci
)
{
EFI_STATUS Status;
Status = PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationEnable,
EFI_PCI_DEVICE_ENABLE,
NULL
);
ASSERT_EFI_ERROR (Status);
if (!mDetectVgaOnly) {
//
// Here we decide whether it is LPC Bridge
//
if ((IS_PCI_LPC (Pci)) ||
((IS_PCI_ISA_PDECODE (Pci)) &&
(Pci->Hdr.VendorId == 0x8086)
)
) {
//
// Add IsaKeyboard to ConIn,
// add IsaSerial to ConOut, ConIn, ErrOut
//
DEBUG ((EFI_D_INFO, "Found LPC Bridge device\n"));
PrepareLpcBridgeDevicePath (Handle);
return EFI_SUCCESS;
}
//
// Here we decide which Serial device to enable in PCI bus
//
if (IS_PCI_16550SERIAL (Pci)) {
//
// Add them to ConOut, ConIn, ErrOut.
//
DEBUG ((EFI_D_INFO, "Found PCI 16550 SERIAL device\n"));
PreparePciSerialDevicePath (Handle);
return EFI_SUCCESS;
}
}
//
// Here we decide which VGA device to enable in PCI bus
//
if (IS_PCI_VGA (Pci)) {
//
// Add them to ConOut.
//
DEBUG ((EFI_D_INFO, "Found PCI VGA device\n"));
PreparePciVgaDevicePath (Handle);
return EFI_SUCCESS;
}
return Status;
}
/**
Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut
@param[in] DetectVgaOnly - Only detect VGA device if it's TRUE.
@retval EFI_SUCCESS - PCI Device check and Console variable update successfully.
@retval EFI_STATUS - PCI Device check or Console variable update fail.
**/
EFI_STATUS
DetectAndPreparePlatformPciDevicePaths (
BOOLEAN DetectVgaOnly
)
{
mDetectVgaOnly = DetectVgaOnly;
return VisitAllPciInstances (DetectAndPreparePlatformPciDevicePath);
}
/**
The function will connect root bridge
@return EFI_SUCCESS Connect RootBridge successfully.
**/
EFI_STATUS
ConnectRootBridge (
VOID
)
{
EFI_STATUS Status;
EFI_HANDLE RootHandle;
//
// Make all the PCI_IO protocols on PCI Seg 0 show up
//
Status = gBS->LocateDevicePath (
&gEfiDevicePathProtocolGuid,
&gPlatformRootBridges[0],
&RootHandle
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->ConnectController (RootHandle, NULL, NULL, FALSE);
if (EFI_ERROR (Status)) {
return Status;
}
return EFI_SUCCESS;
}
/**
Platform console init. Include the platform firmware vendor, revision
and so crc check.
**/
VOID
EFIAPI
PlatformConsoleInit (
VOID
)
{
gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
gUartDeviceNode.Parity = PcdGet8 (PcdUartDefaultParity);
gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
ConnectRootBridge ();
//
// Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut
//
DetectAndPreparePlatformPciDevicePaths (FALSE);
}

70
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h
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@ -1,70 +0,0 @@
/** @file
Head file for BDS Platform specific code
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PLATFORM_CONSOLE_H
#define _PLATFORM_CONSOLE_H
#include <PiDxe.h>
#include <IndustryStandard/Pci.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Library/DevicePathLib.h>
#include <Protocol/PciIo.h>
#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
//
// Type definitions
//
//
// Platform Root Bridge
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
typedef
EFI_STATUS
(EFIAPI *PROTOCOL_INSTANCE_CALLBACK)(
IN EFI_HANDLE Handle,
IN VOID *Instance,
IN VOID *Context
);
/**
@param[in] Handle - Handle of PCI device instance
@param[in] PciIo - PCI IO protocol instance
@param[in] Pci - PCI Header register block
**/
typedef
EFI_STATUS
(EFIAPI *VISIT_PCI_INSTANCE_CALLBACK)(
IN EFI_HANDLE Handle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN PCI_TYPE00 *Pci
);
/**
Platform console init. Include the platform firmware vendor, revision
and so crc check.
**/
VOID
EFIAPI
PlatformConsoleInit (
VOID
);
#endif

19
CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c
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@ -1,19 +0,0 @@
/**@file
Defined the platform specific device path which will be filled to
ConIn/ConOut variables.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PlatformBootManager.h"
///
/// Predefined platform default console device path
///
PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
{
NULL,
0
}
};

105
CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
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@ -1,105 +0,0 @@
/** @file
Platform Hook Library instance for UART device upon coreboot.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Uefi/UefiBaseType.h>
#include <Library/PciLib.h>
#include <Library/PlatformHookLib.h>
#include <Library/CbParseLib.h>
#include <Library/PcdLib.h>
typedef struct {
UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
UINT16 DeviceId; ///< Device ID to match the PCI device
UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
UINT64 Offset; ///< The byte offset into to the BAR
UINT8 BarIndex; ///< Which BAR to get the UART base address
UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT8 Reserved[2];
} PCI_SERIAL_PARAMETER;
/**
Performs platform specific initialization required for the CPU to access
the hardware associated with a SerialPortLib instance. This function does
not initialize the serial port hardware itself. Instead, it initializes
hardware devices that are required for the CPU to access the serial port
hardware. This function may be called more than once.
@retval RETURN_SUCCESS The platform specific initialization succeeded.
@retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
**/
RETURN_STATUS
EFIAPI
PlatformHookSerialPortInitialize (
VOID
)
{
RETURN_STATUS Status;
UINT32 SerialRegBase;
UINT32 SerialRegAccessType;
UINT32 BaudRate;
UINT32 RegWidth;
UINT32 InputHertz;
UINT32 PayloadParam;
UINT32 DeviceVendor;
PCI_SERIAL_PARAMETER *SerialParam;
Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType,
&RegWidth, &BaudRate, &InputHertz,
&PayloadParam);
if (RETURN_ERROR (Status)) {
return Status;
}
if (SerialRegAccessType == 2) { //MMIO
Status = PcdSetBoolS (PcdSerialUseMmio, TRUE);
} else { //IO
Status = PcdSetBoolS (PcdSerialUseMmio, FALSE);
}
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet64S (PcdSerialRegisterBase, (UINT64) SerialRegBase);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet32S (PcdSerialRegisterStride, RegWidth);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet32S (PcdSerialBaudRate, BaudRate);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet32S (PcdSerialClockRate, InputHertz);
if (RETURN_ERROR (Status)) {
return Status;
}
if (PayloadParam >= 0x80000000) {
DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000);
SerialParam = PcdGetPtr(PcdPciSerialParameters);
SerialParam->VendorId = (UINT16)DeviceVendor;
SerialParam->DeviceId = DeviceVendor >> 16;
SerialParam->ClockRate = InputHertz;
SerialParam->RegisterStride = (UINT8)RegWidth;
}
return RETURN_SUCCESS;
}

39
CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
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@ -1,39 +0,0 @@
## @file
# Platform Hook Library instance for UART device upon coreboot.
#
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformHookLib
FILE_GUID = 40A2CBC6-CFB8-447b-A90E-198E88FD345E
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformHookLib
CONSTRUCTOR = PlatformHookSerialPortInitialize
[Sources]
PlatformHookLib.c
[LibraryClasses]
CbParseLib
PcdLib
PciLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
CorebootModulePkg/CorebootModulePkg.dec
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES

221
CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c
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@ -1,221 +0,0 @@
/** @file
Reset System Library functions for coreboot
Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Guid/AcpiBoardInfoGuid.h>
VOID
AcpiPmControl (
UINTN SuspendType
)
{
EFI_HOB_GUID_TYPE *GuidHob;
ACPI_BOARD_INFO *pAcpiBoardInfo;
UINTN PmCtrlReg = 0;
ASSERT (SuspendType <= 7);
//
// Find the acpi board information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
PmCtrlReg = (UINTN)pAcpiBoardInfo->PmCtrlRegBase;
IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (SuspendType << 10));
IoOr16 (PmCtrlReg, BIT13);
CpuDeadLoop ();
}
/**
Calling this function causes a system-wide reset. This sets
all circuitry within the system to its initial state. This type of reset
is asynchronous to system operation and operates without regard to
cycle boundaries.
System reset should not return, if it returns, it means the system does
not support cold reset.
**/
VOID
EFIAPI
ResetCold (
VOID
)
{
EFI_HOB_GUID_TYPE *GuidHob;
ACPI_BOARD_INFO *pAcpiBoardInfo;
//
// Find the acpi board information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
IoWrite8 ((UINTN)pAcpiBoardInfo->ResetRegAddress, pAcpiBoardInfo->ResetValue);
CpuDeadLoop ();
}
/**
Calling this function causes a system-wide initialization. The processors
are set to their initial state, and pending cycles are not corrupted.
System reset should not return, if it returns, it means the system does
not support warm reset.
**/
VOID
EFIAPI
ResetWarm (
VOID
)
{
EFI_HOB_GUID_TYPE *GuidHob;
ACPI_BOARD_INFO *pAcpiBoardInfo;
//
// Find the acpi board information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
IoWrite8 ((UINTN)pAcpiBoardInfo->ResetRegAddress, pAcpiBoardInfo->ResetValue);
CpuDeadLoop ();
}
/**
Calling this function causes the system to enter a power state equivalent
to the ACPI G2/S5 or G3 states.
System shutdown should not return, if it returns, it means the system does
not support shut down reset.
**/
VOID
EFIAPI
ResetShutdown (
VOID
)
{
EFI_HOB_GUID_TYPE *GuidHob;
ACPI_BOARD_INFO *pAcpiBoardInfo;
UINTN PmCtrlReg;
//
// Find the acpi board information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
//
// GPE0_EN should be disabled to avoid any GPI waking up the system from S5
//
IoWrite16 ((UINTN)pAcpiBoardInfo->PmGpeEnBase, 0);
//
// Clear Power Button Status
//
IoWrite16((UINTN) pAcpiBoardInfo->PmEvtBase, BIT8);
//
// Transform system into S5 sleep state
//
PmCtrlReg = (UINTN)pAcpiBoardInfo->PmCtrlRegBase;
IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (7 << 10));
IoOr16 (PmCtrlReg, BIT13);
CpuDeadLoop ();
ASSERT (FALSE);
}
/**
Calling this function causes the system to enter a power state for capsule
update.
Reset update should not return, if it returns, it means the system does
not support capsule update.
**/
VOID
EFIAPI
EnterS3WithImmediateWake (
VOID
)
{
AcpiPmControl (5);
ASSERT (FALSE);
}
/**
This function causes a systemwide reset. The exact type of the reset is
defined by the EFI_GUID that follows the Null-terminated Unicode string passed
into ResetData. If the platform does not recognize the EFI_GUID in ResetData
the platform must pick a supported reset type to perform.The platform may
optionally log the parameters from any non-normal reset that occurs.
@param[in] DataSize The size, in bytes, of ResetData.
@param[in] ResetData The data buffer starts with a Null-terminated string,
followed by the EFI_GUID.
**/
VOID
EFIAPI
ResetPlatformSpecific (
IN UINTN DataSize,
IN VOID *ResetData
)
{
ResetCold ();
}
/**
The ResetSystem function resets the entire platform.
@param[in] ResetType The type of reset to perform.
@param[in] ResetStatus The status code for the reset.
@param[in] DataSize The size, in bytes, of ResetData.
@param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
the data buffer starts with a Null-terminated string, optionally
followed by additional binary data. The string is a description
that the caller may use to further indicate the reason for the
system reset.
**/
VOID
EFIAPI
ResetSystem (
IN EFI_RESET_TYPE ResetType,
IN EFI_STATUS ResetStatus,
IN UINTN DataSize,
IN VOID *ResetData OPTIONAL
)
{
switch (ResetType) {
case EfiResetWarm:
ResetWarm ();
break;
case EfiResetCold:
ResetCold ();
break;
case EfiResetShutdown:
ResetShutdown ();
return;
case EfiResetPlatformSpecific:
ResetPlatformSpecific (DataSize, ResetData);
return;
default:
return;
}
}

38
CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf
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@ -1,38 +0,0 @@
## @file
# Library instance for ResetSystem library class for coreboot
#
# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ResetSystemLib
FILE_GUID = C5CD4EEE-527F-47df-9C92-B41414AF7479
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ResetSystemLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
ResetSystemLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
CorebootModulePkg/CorebootModulePkg.dec
[LibraryClasses]
DebugLib
IoLib
HobLib
[Guids]
gUefiAcpiBoardInfoGuid