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MdeModulePkg/NvmExpressDxe: Handling return of write to sq and cq db 

In case of an async command if updating the submission queue tail
doorbell fails then the command will not be picked up by device and
no completion response will be created. This scenario has to be handled.
Also if we create an AsyncRequest element and insert in the async queue,
it will never receive a completion so in the timer routine this element
won't be freed, resulting in memory leak. Also in case of blocking calls
we should capture the status of updating completion queue head doorbell
register and return it to caller of PassThru.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Suman Prakash <suman.p@samsung.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Suman Prakash 2017-04-20 18:01:42 +08:00 committed by Hao Wu
parent f8f931f632
commit f6b139bde7
1 changed files with 6 additions and 2 deletions
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8
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c
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@ -603,7 +603,7 @@ NvmExpressPassThru (
Private->SqTdbl[QueueId].Sqt ^= 1;
}
Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);
PciIo->Mem.Write (
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,
@ -612,6 +612,10 @@ NvmExpressPassThru (
&Data
);
if (EFI_ERROR (Status)) {
goto EXIT;
}
//
// For non-blocking requests, return directly if the command is placed
// in the submission queue.
@ -695,7 +699,7 @@ NvmExpressPassThru (
}
Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);
PciIo->Mem.Write (
Status = PciIo->Mem.Write (
PciIo,
EfiPciIoWidthUint32,
NVME_BAR,