ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native mode

The GICv3 driver must use native mode to drive a GICv3 due to
the fact that v2 compatibility is optional in the v3 spec.
However, if v2 compatibility is implemented, it is the default
and needs to be disabled first by setting the Affinity Routing
Enable (ARE) bit.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>

[added PCD that allows forcing the GICv3 driver to drive the GIC in v2 mode]
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Tested-by: Ard Biesheuvel <ard@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16875 6f19259b-4bc3-4df7-8a09-765794883524

ArmPkg/ArmPkg.dec

@@ -69,6 +69,9 @@
   # Linux (instead of PSCI)
   gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
 
+  # Define if the GICv3 controller should use the GICv2 legacy
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 

ArmPkg/Drivers/ArmGic/ArmGicDxe.inf

@@ -1,7 +1,7 @@
 #/** @file
 #
 #  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.<BR>
+#  Copyright (c) 2012 - 2015, ARM Ltd. All rights reserved.<BR>
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -54,6 +54,7 @@
   gArmTokenSpaceGuid.PcdGicDistributorBase
   gArmTokenSpaceGuid.PcdGicRedistributorsBase
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy
 
 [Depex]
   gEfiCpuArchProtocolGuid

ArmPkg/Drivers/ArmGic/ArmGicLib.c

@@ -186,7 +186,7 @@ ArmGicEnableInterrupt (
   RegShift = Source % 32;
 
   Revision = ArmGicGetSupportedArchRevision ();
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
     // Write set-enable register
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);
   } else {
@@ -219,7 +219,7 @@ ArmGicDisableInterrupt (
   RegShift = Source % 32;
 
   Revision = ArmGicGetSupportedArchRevision ();
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
     // Write clear-enable register
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);
   } else {
@@ -252,7 +252,7 @@ ArmGicIsInterruptEnabled (
   RegShift = Source % 32;
 
   Revision = ArmGicGetSupportedArchRevision ();
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
     Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);
   } else {
     GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);

ArmPkg/Drivers/ArmGic/ArmGicLib.inf

@@ -47,3 +47,6 @@
 
 [Pcd]
   gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+[FeaturePcd]
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy

ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf

@@ -48,3 +48,6 @@
 
 [Pcd]
   gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+[FeaturePcd]
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy

ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c

@@ -249,6 +249,14 @@ GicV3DxeInitialize (
   mGicRedistributorsBase = PcdGet32 (PcdGicRedistributorsBase);
   mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
 
+  //
+  // We will be driving this GIC in native v3 mode, i.e., with Affinity
+  // Routing enabled. So ensure that the ARE bit is set.
+  //
+  if (!FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
+    MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE);
+  }
+
   for (Index = 0; Index < mGicNumInterrupts; Index++) {
     GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
 

ArmPkg/Include/Library/ArmGicLib.h

@@ -53,6 +53,9 @@ typedef enum {
 // GICv3 specific registers
 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
 
+// the Affinity Routing Enable (ARE) bit in GICD_CTLR
+#define ARM_GIC_ICDDCR_ARE      (1 << 4)
+
 //
 // GIC Redistributor
 //