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UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level paging 

Reserved6 is changed to Reserved7 because the bit width is changed.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ray Ni 2019-04-08 15:32:00 +08:00
parent 7f33d4f228
commit f8113e2500
1 changed files with 5 additions and 2 deletions
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7
UefiCpuPkg/Include/Register/Cpuid.h
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@ -1506,8 +1506,11 @@ typedef union {
/// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
///
UINT32 AVX512_VPOPCNTDQ:1;
UINT32 Reserved6:2;
UINT32 Reserved7:1;
///
/// [Bits 16] Supports 5-level paging if 1.
///
UINT32 FiveLevelPage:1;
///
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
/// in 64-bit mode.