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UefiCpuPkg/PiSmmCpuDxeSmm: Use public MSR_IA32_MISC_ENABLE definition 

Use the MSR MSR_IA32_MISC_ENABLE definition defined in UefiCpuPkg/Include and
remove the local definition.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Jeff Fan 2016-04-08 13:55:14 +08:00 committed by Michael Kinney
parent 846704334c
commit f85d3ce2ef
4 changed files with 23 additions and 21 deletions
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25
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@ -1013,13 +1013,14 @@ SmiRendezvous (
IN UINTN CpuIndex
)
{
EFI_STATUS Status;
BOOLEAN ValidSmi;
BOOLEAN IsBsp;
BOOLEAN BspInProgress;
UINTN Index;
UINTN Cr2;
BOOLEAN XdDisableFlag;
EFI_STATUS Status;
BOOLEAN ValidSmi;
BOOLEAN IsBsp;
BOOLEAN BspInProgress;
UINTN Index;
UINTN Cr2;
BOOLEAN XdDisableFlag;
MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;
//
// Save Cr2 because Page Fault exception in SMM may override its value
@ -1083,9 +1084,11 @@ SmiRendezvous (
//
XdDisableFlag = FALSE;
if (mXdSupported) {
if ((AsmReadMsr64 (MSR_IA32_MISC_ENABLE) & B_XD_DISABLE_BIT) != 0) {
MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
if (MiscEnableMsr.Bits.XD == 1) {
XdDisableFlag = TRUE;
AsmMsrAnd64 (MSR_IA32_MISC_ENABLE, ~B_XD_DISABLE_BIT);
MiscEnableMsr.Bits.XD = 0;
AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64);
}
ActivateXd ();
}
@ -1176,7 +1179,9 @@ SmiRendezvous (
// Restore XD
//
if (XdDisableFlag) {
AsmMsrOr64 (MSR_IA32_MISC_ENABLE, B_XD_DISABLE_BIT);
MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
MiscEnableMsr.Bits.XD = 1;
AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64);
}
}

3
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@ -1,7 +1,7 @@
/** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -53,6 +53,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <CpuHotPlugData.h>
#include <Register/Cpuid.h>
#include <Register/Msr.h>
#include "CpuService.h"
#include "SmmProfile.h"

10
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
View File

@ -934,8 +934,9 @@ CheckFeatureSupported (
IN OUT VOID *Buffer
)
{
UINT32 RegEax;
UINT32 RegEdx;
UINT32 RegEax;
UINT32 RegEdx;
MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;
if (mXdSupported) {
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
@ -966,9 +967,10 @@ CheckFeatureSupported (
// BTINT bits in the MSR_DEBUGCTLA MSR.
// 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.
//
if (AsmMsrBitFieldRead64 (MSR_IA32_MISC_ENABLE, 11, 11) == 1) {
MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
if (MiscEnableMsr.Bits.BTS == 1) {
//
// BTS facilities is not supported if MSR_IA32_MISC_ENABLE BIT11 is set.
// BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.
//
mBtsSupported = FALSE;
}

6
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
View File

@ -17,12 +17,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include "SmmProfileInternal.h"
///
/// MSR Register Index
///
#define MSR_IA32_MISC_ENABLE 0x1A0
#define B_XD_DISABLE_BIT BIT34
//
// External functions
//